我收到了一份描述我大學RAM的任務。在我看來,我已經編寫了一個代碼來模擬上述設備的行爲。但它似乎並不奏效。VHDL。新值賦值後信號值不會改變
我在下面的方式描述的設備的實體:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
LIBRARY RAM_lib;
USE RAM_lib.RAM_pkg.all;
ENTITY RAM IS
GENERIC(
WORD_LENGTH: INTEGER := 8;
ADDRESS_LENGTH: integer := 8
);
PORT(
Enable : IN std_logic;
DATA_IN : IN std_logic_vector(WORD_LENGTH - 1 downto 0);
DATA_OUT : OUT std_logic_vector(WORD_LENGTH - 1 downto 0);
ADDR : IN std_logic_vector(ADDRESS_LENGTH - 1 downto 0);
RESET : IN std_logic;
CLK : IN std_logic;
WR : IN std_logic;
RD : IN std_logic
);
-- Declarations
END RAM ;
和行爲的部分看起來像:
use work.RAM_pkg.all;
architecture behavior of ram is
---- DATA TYPES DECLARATIONS
-- used type declarations
subtype DATA is std_logic_vector(WORD_LENGTH - 1 downto 0);
subtype ADDRESS is std_logic_vector(ADDRESS_LENGTH - 1 downto 0);
type MEMORY is array (0 to 2**ADDRESS_LENGTH - 1) of DATA;
---- SIGNAL DECLARATION
signal RAM : MEMORY;
begin use work.RAM_pkg.all;
architecture behavior of ram is
---- DATA TYPES DECLARATIONS
-- used type declarations
subtype DATA is std_logic_vector(WORD_LENGTH - 1 downto 0);
subtype ADDRESS is std_logic_vector(ADDRESS_LENGTH - 1 downto 0);
type MEMORY is array (0 to 2**ADDRESS_LENGTH - 1) of DATA;
---- SIGNAL DECLARATION
signal RAM : MEMORY;
begin
-- plug in or plug out ram
plug_in_out: process (enable) is
variable first_load : boolean := true;
begin
if ((enable = '0' and enable'event) or first_load = true) then
data_out <= (others => 'Z');
if (first_load = true) then
first_load := false;
end if;
end if;
end process;
reset_ram: process (reset) is
variable initialized: boolean := false;
begin
if ((reset = '1' and reset'event) or (initialized = false)) then
ram <= (OTHERS => (OTHERS => '0'));
if (initialized = false) then
initialized := true;
end if;
end if;
end process;
-- it serves both "read" and "write" operation for the RAM
read_write: process (clk) is
variable index : integer range 0 to 2**address_length - 1;
begin
if (enable = '1' and clk = '1' and clk'event) then
index := toInt(addr);
if (wr = '1') then
ram(index) <= data_in;
end if;
if (rd = '1') then
data_out <= ram(index);
end if;
end if;
end process;
end architecture behavior;
-- plug in or plug out ram
plug_in_out: process (enable) is
variable first_load : boolean := true;
begin
if ((enable = '0' and enable'event) or first_load = true) then
data_out <= (others => 'Z');
if (first_load = true) then
first_load := false;
end if;
end if;
end process;
reset_ram: process (reset) is
variable initialized: boolean := false;
begin
if ((reset = '1' and reset'event) or (initialized = false)) then
ram <= (OTHERS => (OTHERS => '0'));
if (initialized = false) then
initialized := true;
end if;
end if;
end process;
-- it serves both "read" and "write" operation for the RAM
read_write: process (clk) is
variable index : integer range 0 to 2**address_length - 1;
begin
if (enable = '1' and clk = '1' and clk'event) then
index := toInt(addr);
if (wr = '1') then
ram(index) <= data_in;
end if;
if (rd = '1') then
data_out <= ram(index);
end if;
end if;
end process;
end architecture behavior;
因此,主問題是爲什麼初始化沒有執行,因爲它已在的第5行中指出0進程。代碼的調試表明上述行被執行,但RAM信號的值保持不變。
如果內容在寫入之前無效,爲什麼要初始化RAM?沒有奇偶校驗或ECC存在,'U'或'結果'X會告訴你是否讀取之前未寫入的內存位置,與波形轉儲不同,整個內容不能同時用於封裝設計。 – user1155120
你能詳細解釋一下,你的意思是「如果內容在寫入之前無效,你爲什麼要初始化RAM」。但我不確定我是否清楚地瞭解你。你是否意味着一個寫入操作可能出現在RAM初始化之前? –