VHDL組件輸出返回零

Question

我正在用VHDL寫一篇關於一篇文章的東西，而且我正面臨着一種奇怪的情況。我寫了一些組件，模擬並測試它們，並且一切似乎都正常。但是，在模擬頂級實體時，我會得到零！請看看下面的清單：

頂級實體：

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 

entity foobar is 
    port (data_i : in std_logic_vector(39 downto 0); 
      sum_12bit_o : out std_logic_vector(11 downto 0) 
      ); 
end foobar; 

architecture Behavioral of foobar is 

--Declare components 
component four_10bit_word_adder is 
    port(--Input signals 
      a_byte_in: in std_logic_vector(9 downto 0); 
      b_byte_in: in std_logic_vector(9 downto 0); 
      c_byte_in: in std_logic_vector(9 downto 0); 
      d_byte_in: in std_logic_vector(9 downto 0); 
      cin: in std_logic; 
      --Output signals 
      val12bit_out: out std_logic_vector(11 downto 0) 
    ); 
end component; 

-- Signal declaration 
signal int: std_logic_vector(11 downto 0); 
signal intdata: std_logic_vector(39 downto 0); 

begin 
    intdata <= data_i; --DEBUG 
     U1: four_10bit_word_adder port map (intdata(39 downto 30), intdata(29 downto 20), 
                 intdata(19 downto 10), intdata(9 downto 0), 
               '0', int); 

end Behavioral; 

four_10bit_word_adder：

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 

entity four_10bit_word_adder is 

generic (
    bits: integer := 10 
); 

port(--Input signals 
     a_byte_in: in std_logic_vector(bits-1 downto 0); 
     b_byte_in: in std_logic_vector(bits-1 downto 0); 
     c_byte_in: in std_logic_vector(bits-1 downto 0); 
     d_byte_in: in std_logic_vector(bits-1 downto 0); 
     cin: in std_logic; 
     --Output signals 
     val12bit_out: out std_logic_vector(bits+1 downto 0) 
); 

end four_10bit_word_adder; 

architecture Behavioral of four_10bit_word_adder is 

-- Component Declaration 

component compressor_4_2 is 
    port(a,b,c,d,cin : in std_logic; 
      cout, sum, carry : out std_logic 
     ); 
end component; 

--------------------------------------------------------+ 
component generic_11bit_adder 
port (
    A: in std_logic_vector(10 downto 0); --Input A 
    B: in std_logic_vector(10 downto 0); --Input B 
    CI: in std_logic;       --Carry in 
    O: out std_logic_vector(10 downto 0); --Sum 
    CO: out std_logic       --Carry Out 
); 
end component; 
--------------------------------------------------------+ 

-- Declare internal signals 
signal int: std_logic_vector(bits-1 downto 0); -- int(8) is the final Cout signal 
signal byte_out: std_logic_vector(bits-1 downto 0); 
signal carry: std_logic_vector(bits-1 downto 0); 
signal int11bit: std_logic_vector(bits downto 0); 
-- The following signals are necessary to produce concatenated inputs for the 10-bit adder. 
-- See the paper for more info. 
signal Concat_A: std_logic_vector(bits downto 0); 
signal Concat_B: std_logic_vector(bits downto 0); 
signal co : std_logic; 

begin 

    A0: compressor_4_2 port map (a_byte_in(0), b_byte_in(0), 
           c_byte_in(0), d_byte_in(0), 
           '0', int(0), byte_out(0), carry(0)); 
    instances: for i in 1 to bits-1 generate 
     A: compressor_4_2 port map (a_byte_in(i), b_byte_in(i), 
              c_byte_in(i), d_byte_in(i), int(i-1), 
              int(i), byte_out(i), carry(i)); 
    end generate; 

    R9: generic_11bit_adder port map (Concat_A, Concat_B, '0', int11bit, co); 

Concat_A <= int(8) & byte_out; 
Concat_B <= carry & '0'; 

process (co) 
begin 
    if (co = '1') then 
     val12bit_out <= '1' & int11bit; 
    else 
     val12bit_out <= '0' & int11bit; 
    end if; 
end process; 
end Behavioral; 

4：2壓縮

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 

entity compressor_4_2 is 

    port(a,b,c,d,cin : in std_logic; 
      cout, sum, carry : out std_logic 
); 

end compressor_4_2; 

architecture Behavioral of compressor_4_2 is 

-- Internal Signal Definitions 
signal stage_1: std_logic; 

begin 

stage_1 <= d XOR (b XOR c); 
cout <= NOT((b NAND c) AND (b NAND d) AND (c NAND d)); 
sum <= (a XOR cin) XOR stage_1; 
carry <= NOT((a NAND cin) AND (stage_1 NAND cin) AND (a NAND stage_1)); 

end Behavioral; 

通用11位加法：

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 

entity generic_11bit_adder is 
    generic (
    bits: integer := 11 
); 
    port (
    A: in std_logic_vector(bits-1 downto 0); 
    B: in std_logic_vector(bits-1 downto 0); 
    CI: in std_logic; 
    O: out std_logic_vector(bits-1 downto 0); 
    CO: out std_logic 
); 
end entity generic_11bit_adder; 

architecture Behavioral of generic_11bit_adder is 
begin 

process(A,B,CI) 

    variable sum:   integer; 

    -- Note: we have one bit more to store carry out value. 
    variable sum_vector: std_logic_vector(bits downto 0); 

begin 

    -- Compute our integral sum, by converting all operands into integers. 

    sum := conv_integer(A) + conv_integer(B) + conv_integer(CI); 

    -- Now, convert back the integral sum into a std_logic_vector, of size bits+1 

    sum_vector := conv_std_logic_vector(sum, bits+1); 

    -- Assign outputs 
    O <= sum_vector(bits-1 downto 0); 

    CO <= sum_vector(bits); -- Carry is the most significant bit 

end process; 

end Behavioral; 

我試過一噸的東西，但沒有成功。你有什麼想法我做錯了什麼？對不起，長期的問題，並感謝您的時間。

Answer 1

看看你的過程，在你的four_10bit_word_adder實體中生成val12bit_out。它缺少一個輸入。

另外，還有其他幾個問題。解決這個問題並不能解決所有問題。但是一旦你解決了這個問題，我想事情會變得更加清晰。