2015-09-25 54 views
0

我需要寫這個狀態機控制FIFO數據路徑,但似乎在其他地方被忽略語法錯誤,不要讓我完成正常的狀態機。錯誤:HDLCompiler:806部分被忽略的語法錯誤爲什麼會被忽略?

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 

entity FIFO_FSM is 
    Port (CMD_WR_H : in STD_LOGIC; 
      CMD_RD_H : in STD_LOGIC; 
      SYS_CLK_H : in STD_LOGIC; 
      RST_H : in STD_LOGIC; 
      EMPTY_H : out STD_LOGIC; 
      FULL_H : out STD_LOGIC; 
      LD_EN_0_H : out STD_LOGIC; 
      LD_EN_1_H : out STD_LOGIC; 
      LD_EN_2_H : out STD_LOGIC; 
      LD_EN_3_H : out STD_LOGIC; 
      RD_EN_H : out STD_LOGIC; 
      WR_EN_H : out STD_LOGIC; 
      LD_RVR_H : out STD_LOGIC); 
end FIFO_FSM; 

architecture Behavioral of FIFO_FSM is 
signal PresentState,Nextstate: integer := 0; 
begin 

process(PresentState,CMD_WR_H,CMD_RD_H,RST_H) 
begin 

case PresentState is 

when 0 => -- empty state 
LD_EN_0_H <='0';LD_EN_1_H <='0';LD_EN_2_H <='0';LD_EN_3_H <='0'; 
RD_EN_H<='0';WR_EN_H<='0';LD_RVR_H<='0'; 
EMPTY_H<='1';FULL_H<='0'; 
if(RST_H ='1') then Nextstate<=0; 
elsif(((CMD_WR_H ='1' and CMD_RD_H='1') and (RST_H='0'))) then Nextstate<=0; 
elsif((((CMD_WR_H='0') and (CMD_RD_H='0')) and (RST_H='0')))then Nextstate<=0; 
elsif(((CMD_WR_H='0' and (CMD_RD_H='1')) and (RST_H='0')))then Nextstate<=0; 
elsif((((CMD_WR_H='1') and CMD_RD_H='0') and (RST_H='0')))then Nextstate<=1; 
end if; 

when 1 => --loading Reg 0 transition state 
LD_EN_0_H <='1';LD_EN_1_H <='0';LD_EN_2_H <='0';LD_EN_3_H <='0'; 
RD_EN_H<='0';WR_EN_H<='1';LD_RVR_H<='0'; 
EMPTY_H<='0';FULL_H<='0'; 
Nextstate<=2; 


when 20=> -- unloading R0 
LD_EN_0_H <='1';LD_EN_1_H <='1';LD_EN_2_H <='1';LD_EN_3_H <='1'; 
RD_EN_H<='1';WR_EN_H<='0';LD_RVR_H<='1'; 
EMPTY_H<='0';FULL_H<='0'; 
Nextstate<=0; 

when 2=> -- Reg 0 stored 
LD_EN_0_H <='0';LD_EN_1_H <='0';LD_EN_2_H <='0';LD_EN_3_H <='0'; 
RD_EN_H<='0';WR_EN_H<='0';LD_RVR_H<='0'; 
EMPTY_H<='0';FULL_H<='0'; 
if(RST_H ='1') then Nextstate<=0; 
elsif(((CMD_WR_H ='1' and CMD_RD_H='1') and (RST_H='0'))) then Nextstate<=2; 
elsif((((CMD_WR_H='0') and (CMD_RD_H='0')) and (RST_H='0')))then Nextstate<=2; 
elsif(((CMD_WR_H='0' and (CMD_RD_H='1')) and (RST_H='0')))then Nextstate<=20; 
elsif((((CMD_WR_H='1') and CMD_RD_H='0') and (RST_H='0')))then Nextstate<=3; 
end if; 

when 3=> --Load Reg 1 transition state 
LD_EN_0_H <='0';LD_EN_1_H <='1';LD_EN_2_H <='0';LD_EN_3_H <='0'; 
RD_EN_H<='0';WR_EN_H<='1';LD_RVR_H<='0'; 
EMPTY_H<='0';FULL_H<='0'; 
Nextstate<=4; 

when 42 => --unloading R1 
LD_EN_0_H <='1';LD_EN_1_H <='1';LD_EN_2_H <='1';LD_EN_3_H <='1'; 
RD_EN_H<='1';WR_EN_H<='0';LD_RVR_H<='1'; 
EMPTY_H<='0';FULL_H<='0'; 
Nextstate<=2; 


when 4=> --Reg 1 Stored 
LD_EN_0_H <='0';LD_EN_1_H <='0';LD_EN_2_H <='0';LD_EN_3_H <='0'; 
RD_EN_H<='0';WR_EN_H<='0';LD_RVR_H<='0'; 
EMPTY_H<='0';FULL_H<='0'; 
if(RST_H ='1') then Nextstate<=0; 
elsif(((CMD_WR_H ='1' and CMD_RD_H='1') and (RST_H='0'))) then Nextstate<=4; 
elsif((((CMD_WR_H='0') and (CMD_RD_H='0')) and (RST_H='0')))then Nextstate<=4; 
elsif(((CMD_WR_H='0' and (CMD_RD_H='1')) and (RST_H='0')))then Nextstate<=42; 
elsif((((CMD_WR_H='1') and CMD_RD_H='0') and (RST_H='0')))then Nextstate<=5; 
end if; 

when 5=> --Load Reg 2 transition state 
LD_EN_0_H <='0';LD_EN_1_H <='0';LD_EN_2_H <='1';LD_EN_3_H <='0'; 
RD_EN_H<='0';WR_EN_H<='1';LD_RVR_H<='0'; 
EMPTY_H<='0';FULL_H<='0'; 
Nextstate<=6; 

when 64 -- unloading R2 
LD_EN_0_H <='1';LD_EN_1_H <='1';LD_EN_2_H <='1';LD_EN_3_H <='1'; 
RD_EN_H<='1';WR_EN_H<='0';LD_RVR_H<='1'; 
EMPTY_H<='0';FULL_H<='0'; 
Nextstate<=4; 

when 6=> -- Reg 2 Stored 
LD_EN_0_H <='0';LD_EN_1_H <='0';LD_EN_2_H <='0';LD_EN_3_H <='0'; 
RD_EN_H<='0';WR_EN_H<='0';LD_RVR_H<='0'; 
EMPTY_H<='0';FULL_H<='0'; 
if(RST_H ='1') then Nextstate<=0; 
elsif(((CMD_WR_H ='1' and CMD_RD_H='1') and (RST_H='0'))) then Nextstate<=6; 
elsif((((CMD_WR_H='0') and (CMD_RD_H='0')) and (RST_H='0')))then Nextstate<=6; 
elsif(((CMD_WR_H='0' and (CMD_RD_H='1')) and (RST_H='0')))then Nextstate<=64; 
elsif((((CMD_WR_H='1') and CMD_RD_H='0') and (RST_H='0')))then Nextstate<=7; 
end if; 

when 7=> -- Load Reg 3 transition state 
LD_EN_0_H <='0';LD_EN_1_H <='0';LD_EN_2_H <='0';LD_EN_3_H <='1'; 
RD_EN_H<='0';WR_EN_H<='1';LD_RVR_H<='0'; 
EMPTY_H<='0';FULL_H<='0'; 
Nextstate<=8; 

when 86 -- unloading R3 
LD_EN_0_H <='1';LD_EN_1_H <='1';LD_EN_2_H <='1';LD_EN_3_H <='1'; 
RD_EN_H<='1';WR_EN_H<='0';LD_RVR_H<='1'; 
EMPTY_H<='0';FULL_H<='0'; 
Nextstate<=6; 

when 8=> -- Reg 3 Stored 
LD_EN_0_H <='0';LD_EN_1_H <='0';LD_EN_2_H <='0';LD_EN_3_H <='0'; 
RD_EN_H<='0';WR_EN_H<='0';LD_RVR_H<='0'; 
EMPTY_H<='0';FULL_H<='1'; 
if(RST_H ='1') then Nextstate<=0; 
elsif(((CMD_WR_H ='1' and CMD_RD_H='1') and (RST_H='0'))) then Nextstate<=8; 
elsif((((CMD_WR_H='0') and (CMD_RD_H='0')) and (RST_H='0')))then Nextstate<=8; 
elsif(((CMD_WR_H='0' and (CMD_RD_H='1')) and (RST_H='0')))then Nextstate<=86; 
elsif((((CMD_WR_H='1') and CMD_RD_H='0') and (RST_H='0')))then Nextstate<=8; 
end if; 

end process; 

process(CLK)       -- State Register 
    begin 
     if CLK='1' and CLK'EVENT then  -- rising edge of clock 
     PresentState <= Nextstate; 
    end if; 
    end process; 

end Behavioral; 

我得到這些錯誤:

ERROR:HDLCompiler:806 - "C:/Users/willow/workspaceVHDL/FSM/FIFO_FSM.vhd" Line 96: Syntax error near "<=". 
ERROR:HDLCompiler:806 - "C:/Users/willow/workspaceVHDL/FSM/FIFO_FSM.vhd" Line 119: Syntax error near "<=". 
ERROR:HDLCompiler:806 - "C:/Users/willow/workspaceVHDL/FSM/FIFO_FSM.vhd" Line 135: Syntax error near "process". 

我想要問的是什麼錯誤,以及如何解決它,因爲是說像我不能使用<=來分配對我的投入和產出有價值,但僅限於某些方面,而不是其他方面。我得到的另一個錯誤是在對時鐘敏感的進程之前的最後進程線附近。

+0

它不清楚你在問什麼。請參閱:http://stackoverflow.com/help/how-to-ask瞭解如何提出一個好問題的信息。 – Ian

+0

抱歉,我的第一個問題在這裏,我想問的是錯誤是什麼以及如何解決它,因爲我說我不能使用<=爲我的輸入和輸出分配一個值,但僅在某些行,而不是其他的地方,我得到的另一個錯誤就是在對時鐘敏感的過程之前的結束過程行附近。 – willow

回答

0

首先,你應該格式化你的代碼,使其可讀:

  • 縮進你的代碼相匹配的邏輯層次
  • 在同一行,避免多任務操作員
  • 之間
  • 使用空格

您的代碼可能對你有意義了,但是當你回來這個代碼在幾個月,或者別人必須與它的工作,良好的格式化代碼無線的好處會很快變得明顯。

你的第一和第二錯誤是因爲你有例如when 64,忘記=>。應該說,例如when 64 =>

第三個錯誤是因爲您有case聲明,沒有匹配end case。你的說法應該是這個樣子:

case PresentState is 
    when 0 => 
    -- do something 
    when 1 => 
    -- do something else 
end case; 

這裏的最後一行是你錯過了什麼。

已經解決了case語句的問題,接下來的問題是,您的代碼使用CLK,這不是輸入到你的實體。

接下來的問題是,你的case語句沒有覆蓋所有可能的情況。您可以通過在case語句的末尾添加一個最終when others =>情況下,或通過使用一個枚舉類型的case語句解決這個問題。枚舉類型將是我的選擇,以保持可讀性:

type STATE_MACHINE_type is (IDLE, LOAD_DATA, RESET); 
signal PresentState : STATE_MACHINE_type := IDLE; 

...

case PresentState is 
    when IDLE => 
    Nextstate <= LOAD_DATA; 
    when LOAD_DATA => 
    Nextstate <= RESET; 
    when RESET => 
    Nextstate <= IDLE; 
end case; 

如果你決定使用when others =>方法,但沒有代碼,把在這種情況下,你可以使這個明確使用NULL

case PresentState is 
    when 0 => 
    -- do something 
    when others => 
    NULL; 
end case; 
+0

感謝您的建議,我目前正在上課,但主要是我們必須自己學習語言,因此我的錯誤,因爲我真的沒有找到一個很好的來源來了解語言,就像有很多用於編程語言。 – willow

+0

沒有人開始專家!隨着我建議的更改,您的代碼至少會編譯,所以我認爲這會回答您的問題。 –

+0

非常感謝scary_jeff,我修正了代碼,請問您,我在哪裏可以找到一些適合學習VHDL的教程? – willow