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我會盡力做到完整和具體：Eclipse/OCD中的LPC17xx調試問題
恩智浦LPC1756 Cortex-M3。 Eclipse Helios使用Codesourcery ARM工具鏈和OpenOCD進行調試。 JTAG是Olimex ARM-USB-OCD。操作系統是Windows 7 64位。
我相信我現在已經解決了閃存上傳方面的問題。編程後，我有腳本執行dump_image和轉儲的圖像看起來大致正確。目前我有驗證問題，需要整理，但在這個階段，看起來我的JTAG設置正在工作，並且我正在成功與'1756進行通信。
但是，當我嘗試調試時遇到問題。首先，我的CFG文件，開始與我的目標設備的CFG文件：
# NXP LPC1756 Cortex-M3 with 256kB Flash and 32kB SRAM
debug_level 2
# LPC17xx chips support both JTAG and SWD transports.
# Adapt based on what transport is active.
#source [find swj-dp.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME lpc1756
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists CCLK ] } {
set _CCLK $CCLK
} else {
set _CCLK 4000
}
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x4ba00477
}
jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000
$_TARGETNAME configure -work-area-backup 0
#$_TARGETNAME configure -endian $_ENDIAN
#$_TARGETNAME configure -variant ARMv7
#delays on reset lines
adapter_nsrst_delay 200
jtag_ntrst_delay 200
#reset_config srst_only
#reset_config trst_and_srst srst_pulls_trst
# LPC1756 has 256kB of flash memory, managed by ROM code (including a
# boot loader which verifies the flash exception table's checksum).
# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 0x40000 0 0 $_TARGETNAME \
lpc1700 $_CCLK calc_checksum
# Run with *real slow* clock by default since the
# boot rom could have been playing with the PLL, so
# we have no idea what clock the target is running at.
jtag_khz 50
#$_TARGETNAME configure -event reset-init {
# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
# "User Flash Mode" where interrupt vectors are _not_ remapped,
# and reside in flash instead).
#
# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
# Bit Symbol Value Description Reset
# value
# 0 MAP Memory map control. 0
# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
# 1 User mode. The on-chip Flash memory is mapped to address 0.
# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
#
# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
#MEMMAP - set user mode
# mww 0x400FC040 0x01
#}
$_TARGETNAME configure -event reset-init {
# Force target into ARM state
#armv4_5 core_state arm
#do not remap 0x0000-0x0020 to anything but the flash
#mwb 0xE01FC040 0x01
mwb 0x400FC040 0x01
#mwb 0xE000ED08 0x00
}
現在，我的調試CFG文件：
#define our ports
#telnet_port 4444
#gdb_port 3333
#commands specific to the Olimex ARM-USB-OCD
interface ft2232
ft2232_device_desc "Olimex OpenOCD JTAG A"
ft2232_layout "olimex-jtag"
ft2232_vid_pid 0x15BA 0x0003
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME lpc1756
}
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x4ba00477
}
if { [info exists CCLK ] } {
set _CCLK $CCLK
} else {
set _CCLK 4000
}
if { [info exists ENDIAN ] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
debug_level 3
jtag_khz 100
#delays on reset lines
adapter_nsrst_delay 200
jtag_ntrst_delay 200
#reset_config srst_only
reset_config trst_and_srst srst_pulls_trst
jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
#target cortex_m3 little 0 armv7
set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
#
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000
$_TARGETNAME configure -work-area-backup 0
#working_area 0 0x10000000 0x8000 nobackup
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 0x40000 0 0 $_TARGETNAME lpc1700 $_CCLK calc_checksum
$_TARGETNAME configure -event reset-init {
# Force target into ARM state
#armv4_5 core_state arm
#do not remap 0x0000-0x0020 to anything but the flash
mwb 0xE01FC040 0x01
mwb 0x400FC040 0x01
mwb 0xE000ED08 0x00
}
gdb_flash_program enable
init
#fast enable
jtag_khz 100
debug_level 1
在Eclipse中，我調用這個工具與標誌：
-f arm-usb-ocd.cfg -f debug.cfg
這似乎工作正常（至少我似乎沒有在控制檯中得到任何錯誤）。現在我有問題的部分：
我已經在GDB硬件調試下的Eclipse（Run> Debug Configurations ...）中創建了一個調試配置。相關參數：
Main:
C/C++ Application: output\project_UT1.elf
Debugger:
C:\CodeSourcery\bin\arm-none-eabi-gdb.exe
Startup:
Reset and Delay checked (2-seconds)
Halt checked
Initialization commands:
target remote localhost:3333
monitor flash device = LPC1756
monitor flash download = 1
monitor flash breakpoints = 1
monitor endian little
monitor speed 100
monitor speed auto
monitor reset halt
monitor writeu32 0x400FC040 = 0x00000001
monitor clrbp
Load image: not checked
Load symbols: checked
Runtime options: none of Set program counter, set breakpoint or resume checked
Run commands:
monitor reg sp = 0x10001ffc
monitor reg pc = 0x00001278
continue
Using "Standard GDB Hardware Debugging Launcher"
（注：我已經得到了PC設置爲0x00001278因爲這是我的Reset_Handler的地址，我知道它應該是0x00000004，但我嘗試;當它是0x00000004我得到了同樣的問題...）
當我嘗試使用此設置進行調試時，我收到一條消息，指出「GDB Hardware Debugging Suspended」，PC似乎在bootloader 0x1FFF0080處，我的調試器似乎不再連接。在控制檯中我看到的東西，如：
.
.
.
target remote localhost:3333
0x1fff0080 in ??()
.
.
.
continue
Program received signal SIGINT, Interrupt.
0x1fff0080 in ??()
例如，在反彙編窗口，我可以搜索並找到像「主」或「Reset_Handler」，但拆裝所有「MOVS R0，R0」 - 全部爲零，基本上。我不能單步執行（顯然，暫停...）即使在0x1fff0080，它也顯示「」movs r0，r0「，我似乎可以讀取CPU寄存器（例如sp顯示0x10001ffc，pc顯示0x1fff0081）也許JTAG接口是不是死了......）
我的閃光圖像應該是在00000000（即量表存在）。當我做了dump_image，它出現在設備被編程和矢量如果是這樣，我該如何做一個顯然成功的「轉儲+映像」？
但是，即使在沒有連接JTAG的情況下插入設備也不會導致操作。對於LPC1768這個，但沒有找到任何適合我的東西建議非常感謝。
該死的。很簡單：監控重置init修復它。我不知道我指定的事件是「reset init」，而我的調試器配置從來沒有這樣做過。至於負載，否：在調試其他測試之前，我使用不同的腳本上傳到閃存，所以我只加載符號。非常感謝。 – Mike