輸入變爲零後如何保持相同的FSM狀態？ （SystemVerilog）

Question

我正在嘗試使FSM根據按下的按鈕打開LED矩陣上的不同LED。但是，LED不會保持亮起，鬆開按鈕後，第一個LED將再次亮起。 下面是代碼：

module OneLed(input logic clk, reset, input logic [1:0] button, 
      output logic [7:0] rows, 
      output logic shcp, stcp, mr, oe, ds); //The LED matrix has 3 74hc595 shift registers below it 

     logic [7:0] [23:0] in; 
     logic [1:0] butreg; // thought a register would remember the button input 
     assign butreg = button; 

     //FSM 
     typedef enum logic [1:0] {S0, S1, S2} statetype; 
     statetype state , nextstate; 

    //state register 
    always_ff @(posedge clk, posedge reset) 
      if (reset) state <= S0; 
      else state <= nextstate; 

    //next state logic 
      always_comb 
       case(butreg) 
        S0: if (2'b01) nextstate = S1; 
         else if (2'b10) nextstate = S2; 
         else nextstate = S0; 

        S1: if (2'b01) nextstate = S2; 
         else if (2'b10) nextstate = S0; 
         else nextstate = S1; 

        S2: if (2'b01) nextstate = S0; 
         else if (2'b10) nextstate = S1; 
         else nextstate = S2;  
        default: nextstate = S0; 
      endcase 

    //output logic 
    always_comb 
      begin 
       if (state == S0) 
        in [0] = 24'b10000000_00000000_00000000; 
       else if (state == S1) 
        in [0] = 24'b00000000_10000000_00000000; 
       else if (state == S2)   
        in[0] = 24'b00000000_00000000_10000000; 
    end   

    led LED (clk, in , rows, shcp, stcp, mr, oe, ds); // this module works fine 
endmodule 

Answer 1

assign butreg = button; 

此語句對待butreg爲線材，即直接連接到輸入信號按鈕。

如果您正在尋找按鈕的數值鎖存到寄存器butreg，則需要在適當的情況下（posedge時鐘或*或其他一些條件使用總是塊和觸發。

例如，替代上述分配，你可能有

always @(posedge clk) begin 
    if (button == 2'b00) begin 
    butreg <= butreg; 
    end 
    else begin 
    butreg <= button; 
    end 
end