什麼是makefile的C++的

Question

格式我以前用過類似

g++ myfile.cpp -o myoutput 

命令來編譯我的C++代碼，但我想轉移到使用的makefile。所以我不知道天氣我聽起來愚蠢或不是，製造文件的簡單格式是什麼

就像我有一個名爲template.cpp的cpp文件，我該如何編譯它使用make？

Answer 1

最簡單的makefile，你問什麼，看起來是這樣的：

myfile: myfile.cpp 
    g++ myfile.cpp -o myfile 

請注意，這是第二行的硬標籤。如果你在一個名爲makefile的文件中有這個，那麼你可以從終端運行make來編譯你的代碼。

順便說一句，this是寫makefiles的絕好教程 - 非常值得一讀。

Answer 2

我推薦你這個鏈接。它向你介紹輕鬆學習如何爲CPP做的makefile makefiles easy

我也建議您在此模板，我弗朗在這裏使用template

# A sample Makefile 
# This Makefile demonstrates and explains 
# Make Macros, Macro Expansions, 
# Rules, Targets, Dependencies, Commands, Goals 
# Artificial Targets, Pattern Rule, Dependency Rule. 

# Comments start with a # and go to the end of the line. 

# Here is a simple Make Macro. 
LINK_TARGET = test_me.exe 

# Here is a Make Macro that uses the backslash to extend to multiple lines. 
OBJS = \ 
Test1.o \ 
Test2.o \ 
Main.o 

# Here is a Make Macro defined by two Macro Expansions. 
# A Macro Expansion may be treated as a textual replacement of the Make Macro. 
# Macro Expansions are introduced with $ and enclosed in (parentheses). 
REBUILDABLES = $(OBJS) $(LINK_TARGET) 

# Here is a simple Rule (used for "cleaning" your build environment). 
# It has a Target named "clean" (left of the colon ":" on the first line), 
# no Dependencies (right of the colon), 
# and two Commands (indented by tabs on the lines that follow). 
# The space before the colon is not required but added here for clarity. 
clean : 
    rm -f $(REBUILDABLES) 
    echo Clean done 

# There are two standard Targets your Makefile should probably have: 
# "all" and "clean", because they are often command-line Goals. 
# Also, these are both typically Artificial Targets, because they don't typically 
# correspond to real files named "all" or "clean". 

# The rule for "all" is used to incrementally build your system. 
# It does this by expressing a dependency on the results of that system, 
# which in turn have their own rules and dependencies. 
all : $(LINK_TARGET) 
    echo All done 

# There is no required order to the list of rules as they appear in the Makefile. 
# Make will build its own dependency tree and only execute each rule only once 
# its dependencies' rules have been executed successfully. 

# Here is a Rule that uses some built-in Make Macros in its command: 
# $@ expands to the rule's target, in this case "test_me.exe". 
# $^ expands to the rule's dependencies, in this case the three files 
# main.o, test1.o, and test2.o. 
$(LINK_TARGET) : $(OBJS) 
    g++ -g -o $@ $^ 

# Here is a Pattern Rule, often used for compile-line. 
# It says how to create a file with a .o suffix, given a file with a .cpp suffix. 
# The rule's command uses some built-in Make Macros: 
# $@ for the pattern-matched target 
# $< for the pattern-matched dependency 
%.o : %.cpp 
    g++ -g -o $@ -c $< 

# These are Dependency Rules, which are rules without any command. 
# Dependency Rules indicate that if any file to the right of the colon changes, 
# the target to the left of the colon should be considered out-of-date. 
# The commands for making an out-of-date target up-to-date may be found elsewhere 
# (in this case, by the Pattern Rule above). 
# Dependency Rules are often used to capture header file dependencies. 
Main.o : Main.h Test1.h Test2.h 
Test1.o : Test1.h Test2.h 
Test2.o : Test2.h 

# Alternatively to manually capturing dependencies, several automated 
# dependency generators exist. Here is one possibility (commented out)... 
# %.dep : %.cpp 
# g++ -M $(FLAGS) $< > $@ 
# include $(OBJS:.o=.dep)