有沒有辦法將字符串強制枚舉在系統verilog中?鑄造字符串枚舉
typedef enum {ABC1,ABC2,ABC3} abc;
program Test ;
abc x1;
string teststring;
initial
begin
teststring="ABC2";
x1=abc'(teststring); // Static cast doesn't work
$display("[%s][%0d]",teststring,x1);
end
endprogram