在同步器上運行測試臺時發生AlwaysError

Question

運行測試臺時出現此錯誤，以及在兩個現有D-FF上構建的同步器。

File "/home/runner/design.py", line 28, in Sync 
    @always_seq(clk.posedge, reset=reset) 
    File "/usr/share/myhdl-0.8/lib/python/myhdl/_always_seq.py", line 76, in _always_seq_decorator 
    raise AlwaysSeqError(_error.ArgType) 
myhdl.AlwaysError: decorated object should be a classic (non-generator) function 

我的測試平臺概述如下

from myhdl import * 
from random import randrange 

HALF_PERIOD = delay(10) ### This makes a 20-ns clock signal 
ACTIVE_HIGH = 1 
G_DELAY = delay(15) 

def Main(): 
### Signal declaration 
    clk, d, dout = [Signal(intbv(0)) for i in range(3)] 
    reset = ResetSignal(1,active=ACTIVE_HIGH,async=True) 


### Module Instantiation 

    S1 = Sync(dout, d, clk,reset) 

### Clk generator 

    @always(HALF_PERIOD) 
    def ClkGen(): 
     clk.next = not clk 


### TB def 
    @instance 
    def Driver(): 
     yield(HALF_PERIOD) 
     reset.next = 0 
     for i in range(4): 
      yield(G_DELAY) 
      d.next = not d 
     raise StopSimulation 

    return ClkGen, Driver, S1 

m1 = traceSignals(Main) 
sim = Simulation(m1) 
sim.run() 

我的同步編碼如下。

from myhdl import * 
from DFF import * 

def Sync(dout,din,clk,reset): 

    """ The module consists of two FFs with one internal signal 

    External signals 

    dout : output 
    din : input 
    clk : input 

    Internal signal: 

    F2F : output-to-input signal that connects two FFs together 

    """ 
### Connectivity 

    F2F = Signal(intbv(0)) 

    F1 = DFF(F2F,din,clk,reset) 
    F2 = DFF(dout,F2F,clk,reset) 

### Function 

    @always_seq(clk.posedge,reset=reset) 
    def SyncLogic(): 
     if reset: 
      F2F.next = 0 
      dout.next = 0 
     else: 
     F2F.next = din 
     yield(WIRE_DELAY) 
     dout.next = F2F 
    return SyncLogic 

和FF原型編碼如下。

from myhdl import * 

def DFF(dout,din,clk,reset): 

    @always_seq(clk.posedge, reset=reset) 
    def Flogic(): 
     if reset: 
      dout.next = 0 
     else: 
      dout.next = din 
    return Flogic 

測試平臺所做的工作與同類測試平臺我較早編碼（略有修改），但結合兩個模塊組合在一起時，它沒有工作。請澄清。謝謝。

Answer 1

要建立導線延遲模型，請使用Signal中的「delay」參數。

變化

@always_seq(clk.posedge,reset=reset) 
def SyncLogic(): 
    if reset: 
     F2F.next = 0 
     dout.next = 0 
    else: 
    F2F.next = din 
    yield(WIRE_DELAY) 
    dout.next = F2F 
return SyncLogic 

到：

dout = Signal(<type>, delay=WIRE_DELAY) 
# ... 
@always_seq(clk.posedge, reset=reset) 
def synclogic(): 
    dout.next = din 

隨着 「always_seq」 不限定復位（它會自動添加）。如果您想明確定義重置用途「@always（clock.posedge，reset.negedge）」。