Verilog中if if else語句中的門實例化

Question

我正在設計使用unisgned比較器模塊的簽名比較器。即如果A和B是4位向量並且

if A[3] ==1 and B[3]==0 then 
    Gout = 0, Eout = 0 and Lout = 1. 
if A[3]==0 and B[3]==1 then 
    Gout = 1, Eout = 0 and Lout = 0; 
else if both A[3] and B[3] are same then 
    the unisigned comparator module has to be instantiated. 

如何在一個if else語句中寫入這個門實例？

module SCOMP(A,B,Great_in,Equal_in,Less_in,Great_out,Equal_out,Less_out); 
    input[3:0] A; 
    input[3:0] B; 
    input Great_in,Equal_in,Less_in; 
    output Great_out,Equal_out,Less_out; 


    reg[3:0] X; 
    reg[3:0] Y; 
    reg p,q,r; 
    wire x,y,z; 
    initial 
    begin 
    X = 0000& A[2:0]; 
    Y = 0000& B[2:0]; 
    end 

    COMP4 g1(X,Y,Gin,Ein,Lin,x,y,z); 

    always @(*) 
    begin 
    if ((A[3]==0)&& (B[3]==1)) 
     begin 
     assign p = 1; 
     assign q = 0; 
     assign r =0; 
     end 
    else if ((A[3]== 1)&&(B[3]==0)) 
     begin 
     assign p = 0; 
     assign q = 0; 
     assign r = 1; 
     end 
    else 
     begin 
     assign p = x; 
     assign q = y; 
     assign r = z; 
     end 
    end 

    assign Great_out = p; 
    assign Equal_out = q; 
    assign Less_out = r; 

endmodule 

Answer 1

Verilog是一個硬件描述語言。硬件既可以存在也可以不存在。實例化任何東西就像將芯片焊接到PCB上一樣。在if語句中實例化東西就像設計一個PCB，其中芯片可以神奇地出現或消失，這取決於PCB的一些輸入。

您的「無符號比較器模塊」必須始終存在 - 它必須無條件地實例化。然後，您需要使用您的if語句來決定是否使用輸出從這個「無符號比較器模塊」或忽略它們，例如：

// the instance of the "unsigned comparator module" 
unsigned_comparator_module UCM (... .gout(ucm_gout), .eout(ucm_eout), .lout(ucm_lout) ...); 

always @* begin 
    if (A[3] == 1 && B[3] == 0) begin 
    Gout = 0; Eout = 0; Lout = 1; 
    end else if (A[3] == 0 && B[3] == 1) begin 
    Gout = 1; Eout = 0; Lout = 0; 
    end else if (A[3] == B[3]) begin 
    Gout = ucm_gout; Eout = ucm_eout; Lout = ucm_lout; 
    end 
end 

Answer 2

做的最好辦法是，如果條件寫的比較裏面的代碼你想要的地方。對於示例

else if both A[3] and B[3] are same then 
    the unisigned comparator module has to be written here.