如何將我的代碼簡化爲一個模塊？

Question

我不知道如何簡化這段代碼，所以它只實例化一次seg7。我是Verilog的新手，所以我沒有任何線索。當前的代碼運行良好，我只需要知道如何簡化它。如果你們都可以善意地看看代碼，告訴我我需要做什麼，我會很高興的讚賞。

module Design (SW, HEX0,HEX1,HEX2,HEX3); 
    input [3:0]SW; 
    output [0:6]HEX0; 
    output [0:6]HEX1; 
    output [0:6]HEX2; 
    output [0:6]HEX3; 

    seg7hex3 disp1(SW[3:0],HEX3); 
    seg7hex2 disp2(SW[3:0],HEX2); 
    seg7hex1 disp3(SW[3:0],HEX1); 
    seg7hex0 disp4(SW[3:0],HEX0); 
endmodule 

module seg7hex3(bcd,leds); 
    input [3:0] bcd; 
    output reg[1:7] leds; 

    always @(bcd) 
     case(bcd) //abcdefg 
      0: leds = 7'b0000000; // b1111111 for active high (B) 
      1: leds = 7'b0110001; // b1001110 (C) 
      3: leds = 7'b0000000; // b1111111 (B) 
      4: leds = 7'b0100100; // b1011011 (S) 
      5: leds = 7'b0001111; // b1110000 (-) 
      6: leds = 7'b0100100; // b1011011 (S) 
      default: leds =7'bx; 
    endcase 

endmodule 

module seg7hex2(bcd,leds); 
    input [3:0] bcd; 
    output reg[1:7] leds; 

    always @(bcd) 
     case(bcd) //abcdefg 
      0: leds = 7'b0001000; // b1110111 for active high (A) 
      1: leds = 7'b1001000; // b0110111 (H) 
      3: leds = 7'b0110000; // b1001111 (E) 
      4: leds = 7'b0000001; // b1111110 (O) 
      5: leds = 7'b0111001; // b1000110 (|) 
      6: leds = 7'b0000001; // b1111110 (O) 
      default: leds =7'bx; 
    endcase 

endmodule 

module seg7hex1(bcd,leds); 
    input [3:0] bcd; 
    output reg[1:7] leds; 

    always @(bcd) 
     case(bcd) //abcdefg 
      0: leds = 7'b1110001; // b0001110 for active high (L) 
      1: leds = 7'b1111001; // b0000110 (I) 
      3: leds = 7'b0110000; // b1001111 (E) 
      4: leds = 7'b0111000; // b1000111 (F) 
      5: leds = 7'b1110001; // b0001110 (first edge half V) 
      6: leds = 7'b1000010; // b0111101 (d) 
      default: leds =7'bx; 
    endcase 

endmodule 

module seg7hex0(bcd,leds); 
    input [3:0] bcd; 
    output reg[1:7] leds; 

    always @(bcd) 
     case(bcd) //abcdefg 
      0: leds = 7'b1110001; // b0001110 for active high (L) 
      1: leds = 7'b0011000; // b1100111 (P) 
      3: leds = 7'b0001000; // b1110111 (R) 
      4: leds = 7'b0001000; // b1110111(A) 
      5: leds = 7'b1000111; // b0111000 (back edge half V) 
      6: leds = 7'b0001000; // b1110111 (A) 
      default: leds =7'bx; 
    endcase 

endmodule 

Answer 1

如何將所有總是在一個模塊（見下文）？這裏是鏈接edaplayground。看起來您正在向所有se7hex模塊傳遞相同的bcd值，所以您可以通過只有一個bcd輸入並將所有始終爲@（bcd）的塊更改爲簡化我的代碼而不是四個bcd輸入。

module Design (SW, HEX0,HEX1,HEX2,HEX3); 
input [3:0]SW; 
output [0:6]HEX0; 
output [0:6]HEX1; 
output [0:6]HEX2; 
output [0:6]HEX3; 

seg7hex3_0 disp_1_4 (
      SW[3:0],HEX3, 
      SW[3:0],HEX2, 
      SW[3:0],HEX1, 
      SW[3:0],HEX0 
      ); 
endmodule 

module seg7hex3_0(
      bcd1,leds1, 
      bcd2,leds2, 
      bcd3,leds3, 
      bcd4,leds4 
      ); 
input [3:0] bcd1, bcd2, bcd3, bcd4; 
output reg[1:7] leds1, leds2, leds3, leds4 ; 

always @(bcd1) 
    case(bcd1) //abcdefg 
     0: leds1 = 7'b0000000; // b1111111 for active high (B) 
     1: leds1 = 7'b0110001; // b1001110 (C) 
     3: leds1 = 7'b0000000; // b1111111 (B) 
     4: leds1 = 7'b0100100; // b1011011 (S) 
     5: leds1 = 7'b0001111; // b1110000 (-) 
     6: leds1 = 7'b0100100; // b1011011 (S) 
     default: leds1 =7'bx; 
endcase 

always @(bcd2) 
    case(bcd2) //abcdefg 
     0: leds2 = 7'b0001000; // b1110111 for active high (A) 
     1: leds2 = 7'b1001000; // b0110111 (H) 
     3: leds2 = 7'b0110000; // b1001111 (E) 
     4: leds2 = 7'b0000001; // b1111110 (O) 
     5: leds2 = 7'b0111001; // b1000110 (|) 
     6: leds2 = 7'b0000001; // b1111110 (O) 
     default: leds2 =7'bx; 
endcase 

always @(bcd3) 
    case(bcd3) //abcdefg 
     0: leds3 = 7'b1110001; // b0001110 for active high (L) 
     1: leds3 = 7'b1111001; // b0000110 (I) 
     3: leds3 = 7'b0110000; // b1001111 (E) 
     4: leds3 = 7'b0111000; // b1000111 (F) 
     5: leds3 = 7'b1110001; // b0001110 (first edge half V) 
     6: leds3 = 7'b1000010; // b0111101 (d) 
     default: leds3 =7'bx; 
endcase 

always @(bcd4) 
    case(bcd4) //abcdefg 
     0: leds4 = 7'b1110001; // b0001110 for active high (L) 
     1: leds4 = 7'b0011000; // b1100111 (P) 
     3: leds4 = 7'b0001000; // b1110111 (R) 
     4: leds4 = 7'b0001000; // b1110111(A) 
     5: leds4 = 7'b1000111; // b0111000 (back edge half V) 
     6: leds4 = 7'b0001000; // b1110111 (A) 
     default: leds4 =7'bx; 
endcase 

endmodule 

如果你只有一個BCD輸入，還可以結合所有情況下，一個總是塊：

always @(bcd) 
    case(bcd) //abcdefg 
      0: begin 
       leds1 = 7'b0000000; // b1111111 for active high (B) 
       leds2 = 7'b0001000; // b1110111 for active high (A) 
       leds3 = 7'b1110001; // b0001110 for active high (L) 
       leds4 = 7'b1110001; // b0001110 for active high (L)\ 
      end 
      1: begin 
       ... 
      end 
      ... 
    endcase