VHDL中的捆綁語句

Question

如何組合/捆綁語句以供進一步使用和更好的處理？例如，這樣的一些任務可能會在將來的例程調用中多次使用。

ADDR_PC  <= "0000000000"; 
ADDR_OP_A <= "00000"; 
ADDR_OP_B <= "00000";    
OP_CODE  <= OP_NOP; 
OP_IMMED <= IMMED_NULL; 
WE_SREG  <= "00000"; -- S V N C Z 

像這樣的東西。

NOP = {ADDR_PC <= "00000000", ADDR_OP_A <= "00000", ...} 

我不知道在VHDL中是否有可能做到這一點。任何提示都會有所幫助。

Answer 1

VHDL有記錄（C叫它struct）。

宣言例如：

type T_MY_RECORD is record 
    Member1 : STD_LOGIC; 
    Member2 : STD_LOGIC_VECTOR(15 downto 0); 
end record; 

signal mySignal1 : T_MY_RECORD; 
signal mySignal2 : T_MY_RECORD; 

使用示例：

mySignal1 <= (
    Member1 => '1', 
    Member2 => x"12FC" 
); 
mySignal2.Member1 <= '0'; 

記錄可以嵌套，例如爲旗子。

Answer 2

記錄和/或聚集體：

library ieee; 
use ieee.std_logic_1164.all; 

entity op_decoded is 
end entity; 

architecture foo of op_decoded is 
    -- These declarations probably want to be in a package 
    constant IMMED_NULL: std_logic_vector (8 downto 0) := (others => '0'); 
    constant OP_NOP:  std_logic_vector (5 downto 0) := (others => '0'); 

    type decode_op is 
     record 
      PC:   std_logic_vector (7 downto 0); 
      OP_A:  std_logic_vector (4 downto 0); 
      OP_B:  std_logic_vector (4 downto 0); 
      OP_CODE: std_logic_vector (5 downto 0); 
      OP_IMMED: std_logic_vector (8 downto 0); 
      WE_SREG: std_logic_vector (4 downto 0); -- S V N C Z 
     end record; 

     constant NOP: decode_op := (
       PC => "00000000", 
       OP_A => "00000", 
       OP_B => "00000", 
       OP_CODE => OP_NOP, 
       OP_IMMED => IMMED_NULL, 
       WE_SREG => "00000" 
      ); 
    -- actual signals 
    signal ADDR_PC: std_logic_vector (7 downto 0); 
    signal ADDR_OP_A: std_logic_vector (4 downto 0); 
    signal ADDR_OP_B: std_logic_vector (4 downto 0); 
    signal OP_CODE: std_logic_vector (5 downto 0); 
    signal OP_IMMED: std_logic_vector (8 downto 0); 
    signal WE_SREG: std_logic_vector (4 downto 0); 

    signal pipe1:  decode_op; 
    signal pipe_disc: decode_op; 

begin 
    (ADDR_PC, ADDR_OP_A, ADDR_OP_B, OP_CODE, OP_IMMED, WE_SREG) <= NOP; 

    pipe1 <= NOP; 

    pipe_disc <= (pipe1.PC, pipe1.OP_A, pipe1.OP_B, pipe1.OP_CODE, 
        pipe1.OP_IMMED, pipe1.WE_SREG); 

end architecture; 

此分析，闡述並模擬（表示它的語法和語義上正確的）。

還有與集料的右手側上的總目標（與設置在型）：

 (ADDR_PC, ADDR_OP_A, ADDR_OP_B, OP_CODE, OP_IMMED, WE_SREG) <= 
    decode_op'(pipe1.PC, pipe1.OP_A, pipe1.OP_B, pipe1.OP_CODE, 
       pipe1.OP_IMMED, pipe1.WE_SREG); 

Answer 3

記錄和/或聚集體是一種可能性，但和替代是在這個過程中，其中聲明一個程序該信號被驅動，然後調用程序，如：

process (clk_i) is 
    procedure NOP is 
    begin 
    ADDR_PC  <= "0000000000"; 
    ADDR_OP_A <= "00000"; 
    ADDR_OP_B <= "00000"; 
    OP_CODE  <= OP_NOP; 
    OP_IMMED <= IMMED_NULL; 
    WE_SREG  <= "00000"; -- S V N C Z 
    end procedure; 
begin 
    if rising_edge(clk_i) then 
    ... 
    NOP; 
    ... 
    end if; 
end process; 

這項工作既爲模擬和綜合代碼。