我正在使用Quartus Prime Pro。
我負責的一個功能,例如:VHDL無法在用戶定義的函數中匹配to_unsigned的調用上下文
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
function round_resize (a : unsigned; b : integer) return unsigned is
variable c : signed (a'length - 1 downto 0); --problem child
variable d : signed (b - 1 downto 0);
begin
c := a + to_signed(2**(b-2), a'length);
d := to_unsigned(c(c'length-2 downto (c'length-b-1)));
return d;
end function;
但我得到的錯誤:
Error(13643): VHDL error at file.vhd(109): can't determine definition of operator ""+"" -- found 0 possible definitions
所以我改變了問題的孩子這樣的:
c := to_unsigned(a + to_signed(2**(b-2), a'length), a'length);
但我得到以下錯誤:
Error(13815): VHDL Qualified Expression error at cpmmod.vhd(110): to_unsigned type specified in Qualified Expression must match signed type that is implied for expression by context
我還可以嘗試做什麼工作?
那麼你可以[尊重類型](https://i.stack.imgur.com/5z9aA.jpg),但它不清楚爲什麼你這樣做。 – user1155120
@ user1155120我真的不明白爲什麼你不把它放在答案中......而是你只是鏈接到一個有答案的代碼圖像!爲什麼儘管所有這些努力,但仍拒絕發佈答案? – JHBonarius