查詢：顯示器上無顯示（VGA CONTROLLER 800 * 600分辨率）BASYS 2 BOARD

Question

我已經爲vga控制器創建了此代碼，並且仿真也是適當的。問題是代碼運行時顯示器爲空，在波形生成中，兩個輸出的hsync和vsync顯示爲'0'。我不知道邏輯出錯的地方。請幫忙。

代碼：

module anymodule(input wire clk,reset, 
output wire hsynch,vsynch, 
output [2:0] red, 
output [2:0] green, 
output [1:0] blue, 
output video_on); 


// defining constants 
localparam HD = 800; // horizontal display area 
localparam HF = 56; // front porch (right border) 
localparam HB = 64; //right porch (left border) 
localparam HR = 120; // horizontal retrace 
localparam VD = 600; // vertical display area 
localparam VF = 37; // front porch (bottom border) 
localparam VB = 23; // back porch (top border) 
localparam VR = 6; // vertical retrace 



//horizontal and vertical counter 
reg [9:0] h_count = 0; 
reg [9:0] v_count = 0; 
wire [9:0] h_end,v_end; 

assign h_end = HD+HF+HR+HB-1; 
assign v_end = VD+VF+VR+VB-1; 


always @(*) begin 
    if(clk) 
    if(h_end) 
     h_count = 0; 
    else 
     h_count = h_count+1; 
    else 
    h_count = h_count; 
end 

always @(posedge clk) begin 
    if(h_end) 
    if(v_count<v_end) 
     v_count = v_count+1; 
    else 
     v_count = 0; 
    else 
    v_count = v_count; 
end 

assign hsynch = ((h_count >= HD+HF-1) && (h_count <= HD+HF+HR+HB-1)); 
assign vsynch = ((v_count >= VD+VF-1) && (v_count <= VD+VF+VR+VB-1)); 
assign video_on = ((h_count < HD)  && (v_count < VD)); 

wire [9:0] pixel_x,pixel_y; 
assign pixel_x = (video_on)? h_count : 10'b0; 
assign pixel_y = (video_on)? v_count : 10'b0; 


reg [7:0] coloroutput; 

always @(clk) 
    if(~video_on) 
    coloroutput <= 0; 
    else begin 
    if(pixel_x<150 && pixel_y<160) 
     coloroutput[7:5] <= 3'b111; 
    else if(pixel_x<250 && pixel_y<320) 
     coloroutput[4:2] <= 3'b111; 
    else 
     coloroutput[1:0] <= 2'b11; 
    end 


assign red = (video_on) ? coloroutput[7:5] : 3'b000; 
assign green = (video_on) ? coloroutput[4:2] : 3'b000; 
assign blue = (video_on) ? coloroutput[1:0] : 3'b000; 


endmodule 

Answer 1

你一定要試試這個模擬。我很肯定你會發現你的代碼在模擬中不起作用。在嘗試編程FPGA之前，始終在模擬環境中檢查您的代碼！你有這條線：

always @(*) begin 
    if(clk) 
    if(h_end) 
     h_count = 0; 

h_end是一個靜態值，你需要將它與某些東西進行比較。也許：

if (h_count == h_end) 

類似的東西。另外，這個總是阻止應該告訴工具尋找時鐘信號的上升沿。例如。

always @(posedge clk) begin 
    if (h_count == h_end)