如何使用gdb轉儲ARM協處理器寄存器？

Question

有沒有辦法從gdb轉儲ARM（特別是CP15 sctlr）的協處理器寄存器？我正在使用源代碼工具鏈（arm-none-linux-gnueabi-）和調試在QEMU上運行的linux。

一種方法可能是在mcr/mrc指令之前/之後轉儲使用過的GPR。有另一種方法嗎？

Answer 1

據我所知，GDB/ARM將無法顯示此信息...但是在調試qemu可以幫助你（假設你可以編譯/調試QEMU其調試信息）：

1. 附加GDB（i686的一定的，但不是ARM）到您的qemu過程
2. 看看這個文件：qemu/target-arm/cpu.h

3. 檢查類似env->cp15或gdbserver_state->g_cpu->cp15 *：

   struct { 
   uint32_t c0_cachetype; 
   uint32_t c0_ccsid[16]; /* Cache size. */ 
   uint32_t c0_clid; /* Cache level. */ 
   uint32_t c0_cssel; /* Cache size selection. */ 
   uint32_t c0_c1[8]; /* Feature registers. */ 
   uint32_t c0_c2[8]; /* Instruction set registers. */ 
   uint32_t c1_sys; /* System control register. */ 
   uint32_t c1_coproc; /* Coprocessor access register. */ 
   uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 
   uint32_t c2_base0; /* MMU translation table base 0. */ 
   uint32_t c2_base1; /* MMU translation table base 1. */ 
   uint32_t c2_control; /* MMU translation table base control. */ 
   uint32_t c2_mask; /* MMU translation table base selection mask. */ 
   uint32_t c2_base_mask; /* MMU translation table base 0 mask. */ 
   uint32_t c2_data; /* MPU data cachable bits. */ 
   uint32_t c2_insn; /* MPU instruction cachable bits. */ 
   uint32_t c3; /* MMU domain access control register 
          MPU write buffer control. */ 
   uint32_t c5_insn; /* Fault status registers. */ 
   uint32_t c5_data; 
   uint32_t c6_region[8]; /* MPU base/size registers. */ 
   uint32_t c6_insn; /* Fault address registers. */ 
   uint32_t c6_data; 
   uint32_t c9_insn; /* Cache lockdown registers. */ 
   uint32_t c9_data; 
   uint32_t c13_fcse; /* FCSE PID. */ 
   uint32_t c13_context; /* Context ID. */ 
   uint32_t c13_tls1; /* User RW Thread register. */ 
   uint32_t c13_tls2; /* User RO Thread register. */ 
   uint32_t c13_tls3; /* Privileged Thread register. */ 
   uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 
   uint32_t c15_ticonfig; /* TI925T configuration byte. */ 
   uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 
   uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 
   uint32_t c15_threadid; /* TI debugger thread-ID. */ 
   } cp15; 
   

*我不知道確切的位置，只是根據qemu/gdbstub.c一些猜測，但我不能夠真正測試。