如何在Verilog中逐行讀取文本文件？

Question

我有一個SREC文件，它是一個簡單的文本文件，我想在verilog中逐行讀取它。我怎樣才能做到這一點？

Answer 1

以下內容通過文件讀取，每個時鐘週期1行：期望的數據格式是每行一個十進制數。

integer    data_file ; // file handler 
integer    scan_file ; // file handler 
logic signed [21:0] captured_data; 
`define NULL 0  

initial begin 
    data_file = $fopen("data_file.dat", "r"); 
    if (data_file == `NULL) begin 
    $display("data_file handle was NULL"); 
    $finish; 
    end 
end 

always @(posedge clk) begin 
    scan_file = $fscanf(data_file, "%d\n", captured_data); 
    if (!$feof(data_file)) begin 
    //use captured_data as you would any other wire or reg value; 
    end 
end 

Answer 2

謝謝你的解決方案。 我對它進行了一些修改，在每行上使用2個包含32個十六進制數字的.txt文件，並且發現了一些困難，因爲我不明白每行代碼的作用。我的發現如下。

只是VAR和暫存器聲明

////////I'm using inputs.txt and outputs.txt to read both lines at the same time 
module Decryption_Top_Testbench; 
////////TEXT DOC variables 

integer    file_outputs ; // var to see if file exists 
integer    scan_outputs ; // captured text handler 
integer    file_inputs  ; // var to see if file exists 
integer    scan_inputs  ; // captured text handler 

//TXT 
reg [127:0] captured_outputs; ///Actual text obtained from outputs.txt lines 
reg [127:0] captured_inputs; ///Actual text obtained from inputs.txt lines 

打開這兩個文件

initial 
begin 

// TEXT FILE outputs/////////////////////// 

    file_outputs = $fopen("C:/outputs.txt", "r"); //Opening text file 

//you should use the full path if you don't want to get in the trouble 
//of using environment vars 

    if (file_outputs == 0) begin    // If outputs file is not found 
     $display("data_file handle was NULL"); //simulation monitor command 
     $finish; 
    end 
    // TEXT FILE inputs/////////////////////// 
    file_inputs = $fopen("C:/inputs.txt", "r"); //Opening text file (inputs) 
     if (file_inputs == 0) begin    //If inputs file is not found 
     $display("data_file handle was NULL"); 
     $finish; 
     end 
end 

在這個部分，我將通過線HEX格式讀取行並將其存儲在「captured_outputs」註冊和「captured_inputs 「註冊。

///Since I'm using it just to simulate I'm not interested on a clock pulse, 
/// I want it to happen all at the same time with whatever comes first 

always @(*) 
begin 

    if (!$feof(file_outputs)) 
    begin 
    ///!$feof means if not reaching the end of file 
    ///file_outputs is always returning a different number other than "0" if the doc 
    ///has not ended. When reaching "0" it means the doc is over. 
    ///Since both of my docs are the same length I'm only validating one of them 
    ///but if you have different lenghts you should verify each doc you're reading 

    /// 

    scan_inputs = $fscanf(file_inputs, "%h\n", captured_inputs);  //Inputs Line text 
    scan_outputs = $fscanf(file_outputs, "%h\n", captured_outputs);  //Outputs line text 

    $display ("Line :[inputs: %h _ outputs: %h ]" captured_inputs, captured_outputs); 
    // Displaying each line at the simulation monitor 

    ///$fscanf means formatted text, $scanf would read text ignoring the format 
    /// %h\n means it should expect HEX numbers and the end of line character, that means 
    /// the line is over, but if you want to use a diff criteria 
    /// you can replace \n to whatever you may need 



    end 

    else 
    begin 

    $finish; 
    $fclose(file_outputs); //Closing files just in case to prevent wasting memory 
    $fclose(file_inputs); 

    end 

end 

我只是想與任何人的東西誰是開始代碼以Verilog能夠理解並重視這個偉大的功能，他/她的項目作出貢獻。

享受！