VHDL方法調用

Question

是否可以編寫代碼段並調用它，而不是多次寫入該段？ IE瀏覽器。我想重用一段代碼，如下所示：

process (currentState) 
begin 
    case currentState is 
    when requiredCoinsTensAnode => anodes <= "100000";--turn on the tens display 
     case tensCount is 
     when "0000" => segDisplay <= "1111110"; --0 
     when "0001" => segDisplay <= "0110000"; --1 
     when "0010" => segDisplay <= "1101101"; --2 
     when "0011" => segDisplay <= "1111001"; --3 
     when "0100" => segDisplay <= "0110011"; --4 
     when "0101" => segDisplay <= "1011011"; --5 
     when "0110" => segDisplay <= "1011111"; --6 
     when "0111" => segDisplay <= "1110000"; --7 
     when "1000" => segDisplay <= "1111111"; --8 
     when others => segDisplay <= "1111011"; --9 
     end case; 
     nextState <= requiredCoinsUnitsAnode;--just displayed the tens digit, next we need to display the units digit 
    when requiredCoinsUnitsAnode => anodes <= "010000";--turn on the units display 
     case unitsCount is 
     when "0000" => segDisplay <= "1111110"; --0 
     when "0001" => segDisplay <= "0110000"; --1 
     when "0010" => segDisplay <= "1101101"; --2 
     when "0011" => segDisplay <= "1111001"; --3 
     when "0100" => segDisplay <= "0110011"; --4 
     when "0101" => segDisplay <= "1011011"; --5 
     when "0110" => segDisplay <= "1011111"; --6 
     when "0111" => segDisplay <= "1110000"; --7 
     when "1000" => segDisplay <= "1111111"; --8 
     when others => segDisplay <= "1111011"; --9 
     end case; 
     nextState <= insertedCoinsTensAnode; 
    end case; 
end process; 

Answer 1

函數是一個選項，因爲拉維指出。

function f_segDisplay (
    signal segCount : std_logic_vector(6 downto 0)) 
    return std_logic_vector(3 downto 0) is 
begin -- f_segDisplay 
    case segCount is 
     when "0000" => return "1111110"; --0 
     when "0001" => return "0110000"; --1 
     when "0010" => return "1101101"; --2 
     when "0011" => return "1111001"; --3 
     when "0100" => return "0110011"; --4 
     when "0101" => return "1011011"; --5 
     when "0110" => return "1011111"; --6 
     when "0111" => return "1110000"; --7 
     when "1000" => return "1111111"; --8 
     when others => return "1111011"; --9 
    end case; 
end f_segDisplay; 

process (currentState, tensCount, unitsCount) 
begin 
    case currentState is 
    when requiredCoinsTensAnode => 
     anodes  <= "100000";   --turn on the tens display 
     segDisplay <= f_segDisplay(tensCount); 
     nextState <= requiredCoinsUnitsAnode; 
    when requiredCoinsUnitsAnode => 
     anodes  <= "010000";   --turn on the units display 
     segDisplay <= f_segDisplay(unitsCount); 
     nextState <= insertedCoinsTensAnode; 
    end case; 
end process; 

根據編譯器和選項的不同，它可能決定將函數代碼放在一行。這會導致放置多個邏輯實例，就像您的原始代碼一樣。

另一種方法是，你把通用代碼出到另一個進程：

p_segdisplay : process (segCount) 
begin -- process p_segdisplay 
    case segCount is 
    when "0000" => segDisplay <= "1111110"; --0 
    when "0001" => segDisplay <= "0110000"; --1 
    when "0010" => segDisplay <= "1101101"; --2 
    when "0011" => segDisplay <= "1111001"; --3 
    when "0100" => segDisplay <= "0110011"; --4 
    when "0101" => segDisplay <= "1011011"; --5 
    when "0110" => segDisplay <= "1011111"; --6 
    when "0111" => segDisplay <= "1110000"; --7 
    when "1000" => segDisplay <= "1111111"; --8 
    when others => segDisplay <= "1111011"; --9 
    end case; 
end process p_segdisplay; 

process (currentState, tensCount, unitsCount) 
begin 
    case currentState is 
    when requiredCoinsTensAnode => 
     anodes <= "100000";   --turn on the tens display 
     segCount <= tensCount; 
     nextState <= requiredCoinsUnitsAnode; 
    when requiredCoinsUnitsAnode => 
     anodes <= "010000";   --turn on the units display 
     segCount <= unitsCount; 
     nextState <= insertedCoinsTensAnode; 
    end case; 
end process; 

BTW：你需要tensCount和unitsCount在你的敏感列表。

抽象這樣的共同資源是一個有用的技術，當做區域或權力意識的設計。

兩者都應該以相同的方式工作，完美的工具將產生相同的邏輯，但我們很少有完美的工具。嘗試不同的風格。有些工具會產生更好的結果，有些則會產生更好的結果

Answer 2

是的，您可以使用VHDL中的函數。

檢查
http://www.pldworld.com/_hdl/1/www.ireste.fr/fdl/vcl/lesd/les_3.htm

Answer 3

該代碼可能是function或procedure中最好的。

entity是用VHDL封裝代碼的另一種方法。