我在使用2位greater than Comparator
和2位equality Comparator
創建4位比較器時遇到麻煩。比比較使用2位Comperator的VHDL 4位Comperator
更大
entity bit2com is
Port (a,b: in STD_LOGIC_vector(1 downto 0);
y : out STD_LOGIC);
end bit2com;
architecture Behavioral of bit2com is
signal p0,p1,p2:std_logic;
begin
p0 <= a(1) and not b(1);
p1 <= a(0) and a(1) and not b(0);
p2<=a(0) and not b(0) and not b(1);
y <= p0 or p1 or p2;
end Behavioral;
平等比較
entity comaeqb is
Port (a,b: in STD_LOGIC_vector(1 downto 0);
y : out STD_LOGIC);
end comaeqb;
architecture Behavioral of comaeqb is
signal p0,p1,p2,p3:std_logic;
begin
p0 <= a(0) and a(1) and b(0) and b(1);
p1 <= a(0) and not a(1) and b(0) and not b(1);
p2<=not a(0) and not a(1) and not b(0) and not b(1);
p3<=not a(0) and a(1) and not b(0) and b(1);
y <= p0 or p1 or p2 or p3;
我如何可以用它來做出比比較大的4位?
將A,B聲明爲numeric_std。[un] signed,並在A> B else'0'時寫入'Y <='1';' –