2011-04-17 57 views
1

我有一個大問題,因爲我沒有正確理解如何使我的功課。 嗯,我必須做這樣的事情:
http://tomaszewicz.zpt.tele.pw.edu.pl/files/u1/zad4.gif
我有代碼創建b1但我不知道如何創建第二個,並使他們連接到b3。創建兩個元素連接到一個多路複用器41和21

我的代碼是:

library ieee; 
use ieee.std_logic_1164.all; 

entity test is 
generic(
n : integer := 4 
); 
port(
a, b, c, d : in std_logic_vector(n-1 downto 0); 
s : in std_logic_vector(1 downto 0); 
y : out std_logic_vector(n-1 downto 0) 
); 
end test; 



-- przypisanie sekwencyjne - case 
architecture arch_mux5 of test is 
begin 
pr_case: process(a,b,c,d,s) 
begin 
case s is 
when "00" => y <= a; 
when "01" => y <= b; 
when "10" => y <= c; 
when others => y <= d; 
end case; 
end process; 
end arch_mux5; 

architecture arch_mux6 of test is 
begin 
pr_if: process(a,b,c,d,s) 
begin 
y <= (others => '0'); -- latch jesli zakomentujemy, dlaczego? 
if s = "00" then 
y <= a; 
end if; 
if s = "01" then 
y <= b; 
end if; 
if s = "10" then 
y <= c; 
end if; 
if s = "11" then 
y <= d; 
end if; 
end process; 
end arch_mux6; 

configuration cfg of test is 
for arch_mux5 
end for; 
end cfg; 

MUX5及MUX6似乎是相同的,但在不同的寫入方法。

回答

3

你必須實例化的多路複用器,例如:

entity top is 
    generic (
    n: integer:=4 
); 
    port (
    a, b, c, d, e, f, g, h: in std_logic_vector(n-1 downto 0); 
    s: in std_logic_vector(2 downto 0); 
    y: out std_logic_vector(n-1 downto 0) 
); 
end entity top; 

architecture struct of top is 
    signal t1, t2: std_logic_vector(n-1 downto 0); 
    component test is 
    generic(
     n : integer := 4 
    ); 
    port (
     a, b, c, d : in std_logic_vector(n-1 downto 0); 
     s : in std_logic_vector(1 downto 0); 
     y : out std_logic_vector(n-1 downto 0) 
    ); 
    end component test; 
    component mux2 is 
    generic(
     n : integer := 4 
    ); 
    port (
     a, b : in std_logic_vector(n-1 downto 0); 
     s : in std_logic; 
     y : out std_logic_vector(n-1 downto 0) 
    ); 
    end component test; 
begin 
    b1: test 
    generic_map (
     n => n 
    ); 
    port map (
     a => a, 
     b => b, 
     c => c, 
     d => d, 
     s => s(1 downto 0), 
     y => t1 
    ); 
    b2: test 
    generic_map (
     n => n 
    ); 
    port map (
     e => a, 
     f => b, 
     g => c, 
     h => d, 
     s => s(1 downto 0), 
     y => t2 
    ); 
    b3: mux2 
    generic_map (
     n => n 
    ); 
    port map (
     a => t1, 
     b => t2, 
     s => s(2), 
     y => y 
    ); 
end architecture struct; 

當然,你仍然要編寫實體+架構mux2。我沒有測試這個代碼(這裏沒有VHDL編譯器),但至少應該引導你進入正確的方向。

+0

謝謝:)我會嘗試 – deadfish 2011-04-19 07:04:10

1

是的,您的老師提供了兩種不同的方式來實現相同的多路複用器。這可能僅用於教育目的。您將需要爲b1和b2實例化此多路複用器。

正如@bmk指出的那樣,您仍然需要爲b3提供一個實現,並在一個頂層實例化這三個多路複用器。

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