-2
VHDL是我遇到過的語法最差的最糟糕的設計語言。 爲什麼這跟選,當代碼給我一個錯誤?:VHDL與選擇時出現錯誤
library ieee;
use ieee.std_logic_1164.all;
entity mux48 is
port(
mux48dv0:in std_logic_vector(7 downto 0);
mux48dv1:in std_logic_vector(7 downto 0);
mux48dv2:in std_logic_vector(7 downto 0);
mux48dv3:in std_logic_vector(7 downto 0);
mux48sv:in std_logic_vector(3 downto 0);
mux48ov:out std_logic_vector(7 downto 0)
);
end mux48;
architectre mux48_df of mux48 is
begin
with mux48sv select
mux48ov <= mux48dv0 when "0000",
<= mux48dv1 when "0001",
<= mux48dv2 when "0010",
<= mux48dv3 when "0011",
<= mux48dv0 when "0100",
<= mux48dv1 when "0101",
<= mux48dv2 when "0110",
<= mux48dv3 when "0111",
<= mux48dv0 when "1000",
<= mux48dv1 when "1001",
<= mux48dv2 when "1010",
<= mux48dv3 when "1011",
<= mux48dv0 when "1100",
<= mux48dv1 when "1101",
<= mux48dv2 when "1110",
<= mux48dv3 when "1111";
end mux48_df;
錯誤:
** Error: C:/Modeltech_pe_edu_10.3/Lab3/mux48.vhd(15): near "architectre": syntax error
VHDL有很多問題和怪癖,但是如果使用得當,它是現場最好的語言。你不會通過苛刻和先發制人地批評你剛剛學習的語言來鼓勵你的問題的答案。 – wjl
那麼哪種語言容忍拼寫錯誤的關鍵字? –
指定16:1多路複用器並將其稱爲Mux4似乎很奇怪。如果你正在進行字節車道轉向並且重新排序是規則的,你可以創建一個select(1 downto 0)信號並將其賦值爲:'mux48sel <= mux48sv(3 downto 2)xor(muxsv(1 downto 0);'You如果重新排序涉及位,它可以按位執行 – user1155120