未簽名的VHDL轉換工作不

Question

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.NUMERIC_STD.ALL; 
-- Uncomment the following library declaration if using 
-- arithmetic functions with Signed or Unsigned values 
--use IEEE.NUMERIC_STD.ALL; 

-- Uncomment the following library declaration if instantiating 
-- any Xilinx primitives in this code. 
--library UNISIM; 
--use UNISIM.VComponents.all; 

entity fourToSixteenDecoder is 
    port (a : in std_logic_vector(0 to 3); 
       EN : in STD_LOGIC; 
       Y : out std_logic_vector(0 to 15)); 
end fourToSixteenDecoder; 

architecture Behavioral of fourToSixteenDecoder is 
begin 
    process(a, EN) 
    variable inputs : integer := conv_integer(unsigned(a)); 
    variable Y_c : std_logic_vector(0 to 15); 
    begin 
     Y_c := X"0000"; 
     if (EN = '1') then 
      Y_c(inputs) := '1'; 
     elsif (EN = '0') then 
      Y_c := X"0000"; 
     end if; 
     Y <= Y_c; 
    end process; 

end Behavioral; 

試圖讓一個4-16譯碼器，不過，我想使用整數和SLV之間的轉換做到位索引分配，但轉換不起作用。

ERROR:HDLCompiler:806 - "..." Line 40: Syntax error near "b". 

也試過

to_integer(unsigned()) 
integer(unsigned()) 
integer(to_unsigned()) 
to_integer(to_unsigned()) 
use IEEE.ARITH and IEEE.STD_LOGIC.UNSIGNED 

無解。

Answer 1

轉換例程在包numeric_std中調用to_integer，對於無符號的轉換例程產生自然範圍整數。

隨着variable inputs : integer := to_integer(unsigned(a));輸入將被初始化爲轉換成整數（可能0如果a是未初始化的（所有'U'多個）a初始值。

沒有其他分配inputsinputs和不會改變與

a值的變化。用

variable inputs: integer range 0 to 15; 

替換變量 inputs聲明

它將輸入範圍限制在索引範圍Y_c。

添加

inputs := to_integer(unsigned(a)); 

作爲第一順序語句的過程。

兩個分配：

 Y_c := X"0000"; 

是冗餘的。 elsif可以消除：

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all; 

entity fourToSixteenDecoder is 
    port ( 
     a: in std_logic_vector(0 to 3); 
     EN: in std_logic; 
     Y: out std_logic_vector(0 to 15) 
    ); 
end entity fourToSixteenDecoder; 

architecture Behavioral of fourToSixteenDecoder is 
begin 
    process(a, EN) 
     -- variable inputs : integer := conv_integer(unsigned(a)); 
     variable inputs: integer range 0 to 15; 
     variable Y_c: std_logic_vector(0 to 15); 
    begin 
     inputs := to_integer(unsigned(a)); -- ADDED 
     Y_c := X"0000"; 
     if EN = '1' then 
      Y_c(inputs) := '1'; 
     -- elsif (EN = '0') then 
     --  Y_c := X"0000"; 
     end if; 
     Y <= Y_c; 
    end process; 
end architecture Behavioral; 

這分析，闡述和模擬。注意if語句條件不需要的括號。

測試平臺：

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all; 

entity tb_4to16 is 
end entity; 

architecture fum of tb_4to16 is 
    signal a: std_logic_vector (0 to 3) := (others => '0'); 
    signal EN: std_logic; 
    signal Y: std_logic_vector(0 to 15); 
begin 
DUT: 
     entity work.fourtosixteendecoder 
     port map (
      a => a, 
      EN => EN, 
      Y => Y 
     ); 
STIMULI: 
    process 
    begin 
     for i in 0 to 15 loop 
      EN <= '0'; 
      a <= std_logic_vector(to_unsigned(i,4)); 
      wait for 10 ns; 
      EN <='1'; 
      wait for 10 ns; 
     end loop; 
     EN <= '0'; 
     wait for 10 ns; 
     wait; 
    end process; 
end architecture; 

結果：