0
module threshold(input[7:0] oLCD_R1,
input[7:0] oLCD_G1,
input[7:0] oLCD_B1,
input[7:0] Rcapture1,
input[7:0] Gcapture1,
input[7:0] Bcapture1,
input oDEN1,
output reg[7:0] oLCD_R2,
output reg[7:0] oLCD_G2,
output reg[7:0] oLCD_B2,
output oDEN2,
output [7:0] Rlower,
output [7:0] Rupper,
output [7:0] Glower,
output [7:0] Gupper,
output [7:0] Blower,
output [7:0] Bupper
);
assign Rlower = Rcapture1;
assign Rupper = Rcapture;
assign oDEN2 = oDEN1;
always @(*)
begin
if (Rcaputre1 < 30)
begin
Rlower = 30;
end
if (Rcaputre1 > 225)
begin
Rupper = 225;
end
end
begin
if (
((Rcapture1 - 30 < oLCD_R1) && (oLCD_R1 < Rcapture1 + 30)) &&
((Gcapture1 - 30 < oLCD_G1) && (oLCD_G1 < Gcapture1 + 30)) &&
((Bcapture1 - 30 < oLCD_B1) && (oLCD_B1 < Bcapture1 + 30))
)
begin
oLCD_R2 = 255;
oLCD_G2 = 192;
oLCD_B2 = 0;
end
else
begin
oLCD_R2 = oLCD_R1;
oLCD_G2 = oLCD_G1;
oLCD_B2 = oLCD_B1;
end
end
endmodule
我試圖防止下溢和溢出期間減法和增加我的Rcapture,但它似乎不能工作,由於對象的'Llower'在左邊的任務錯誤必須有一個網絡類型?我宣佈它作爲一個output reg
爲什麼我還是那麼通過改變聲明防止下溢和溢出
assign Rlower = Rcapture1 ? Rcapture1 < 30 : Rlower == 30;
assign Rupper = Rcapture1 ? Rcapture1 < 225 : Rupper == 225;
assign Glower = Gcapture1 ? Gcapture1 < 30 : Glower == 30;
assign Gupper = Gcapture1 ? Gcapture1 < 225 : Gupper == 225;
assign Blower = Bcapture1 ? Bcapture1 < 30 : Blower == 30;
assign Bupper = Bcapture1 ? Bcapture1 < 225 : Bupper == 225;
這將阻止下溢和溢出的問題得到這個錯誤都Rlower
和Rupper
?
嘗試了你建議的方法,但它仍然不起作用在語句'Rlower = 30'和'Rupper = 225'上出現同樣的錯誤可能是由於沒有在「always」塊中分配它們? – Dom
請參閱:http://quartushelp.altera.com/14.0/mergedProjects/msgs/msgs/evrfx_veri_illegal_continuous_assignment.htm – wilcroft
在'always'塊的開頭附近'Rcapture1 = 30;'行也有錯誤 - '' Rcapture'是一個輸入,不能賦值。 – wilcroft