如何將記錄寫入內存並將其恢復爲VHDL？

Question

在VHDL中的僞代碼我想達到的目的是：

type tTest is record 
    A : std_logic_vector(3 downto 0); 
    B : std_logic_vector(7 downto 0); 
    C : std_logic_vector(0 downto 0); 
end record tTest; 
. . . 
signal sTestIn  : tTest; 
signal sMemWrData : std_logic_vector(fRecordLen(tTest)-1 downto 0); 
signal sMemRdData : std_logic_vector(fRecordLen(tTest)-1 downto 0); 
signal sTestOut  : tTest; 
. . . 
sMemWrData <= fRecordToVector(sTestIn); 
-- At some point sMemRdData gets the data in sMemWrData... 
sTestOut <= fVectorToRecord(sMemRdData); 

fRecordLen是直接從型和fRecordToVector和fVectorToRecord是希望自我解釋返回記錄的聚集長度的假想功能。目標是可合成的代碼，不會產生任何額外的邏輯。我發佈當前的解決方案作爲進一步澄清操作的答案。然而，這是非常尷尬的方法，由於鍋爐板代碼的數量，我不認爲它是一個可行的解決方案。

我知道record introspection proposal但並不屏住呼吸，甚至提出的方法似乎非常繁瑣。

我已經放棄了一個完全一般的解決方案的希望，所以一些讓步是可以接受的。例如，只允許記錄中的std_logic_vectors並使用幾個函數/過程調用。但是，避免使用任何必須手動或根據每個記錄進行外部腳本調整的任何鍋爐代碼將是非常好的。另外，如果有任何可以直接輸入/輸出記錄並且達到相同的Verilog/SystemVerilog包裝，則非常歡迎指針。

Answer 1

這是一種實現要求的方法。評論中有缺點/改進的想法。

library ieee; 
use ieee.std_logic_1164.all; 
package TestPck is 
    type tTest is record 
     A : std_logic_vector(3 downto 0); 
     B : std_logic_vector(7 downto 0); 
     C : std_logic_vector(0 downto 0); 
    end record tTest; 
    procedure pSliceToFrom (
     signal vec_to : out std_logic_vector; 
     signal vec_from : in std_logic_vector; 
     position  : inout integer 
    ); 
end package TestPck; 

package body TestPck is 
    procedure pSliceToFrom (
    signal vec_to : out std_logic_vector; 
    signal vec_from : in std_logic_vector; 
    position  : inout integer 
    ) is 
    begin 
    vec_to <= vec_from(position-1 downto position-vec_to'length); 
    position := position-vec_to'length; 
    end pSliceToFrom; 
end package body TestPck; 

library ieee; 
use ieee.std_logic_1164.all; 
use work.TestPck.all; 

entity tb is 
end entity tb; 

architecture sim of tb is 
    signal sTestIn  : tTest; 
    -- How to create this constant in the package, 
    -- i.e. without needing the signal? 
    constant cTestLength : integer := sTestIn.A'length + sTestIn.B'length + sTestIn.C'length; 
    signal sMemWrData : std_logic_vector(cTestLength-1 downto 0); 
    signal sMemRdData : std_logic_vector(cTestLength-1 downto 0); 
    signal sTestOut  : tTest; 
begin 
    -- How to make this without needing to know what 
    -- is inside tTest? 
    sMemWrData <= sTestIn.A & sTestIn.B & sTestIn.C; 
    -- Memory, Fifo, communication link, doesn't matter... 
    sMemRdData <= sMemWrData after 5 ns; 
    -- How to get the data back without needing this 
    -- process (and the procedure)? 
    slice_data_to_item : process (all) is 
    variable vPosition : integer := 0; 
    begin 
    vPosition := cTestLength; 
    pSliceToFrom(sTestOut.A, sMemRdData, vPosition); 
    pSliceToFrom(sTestOut.B, sMemRdData, vPosition); 
    pSliceToFrom(sTestOut.C, sMemRdData, vPosition); 
    end process slice_data_to_item; 

process is 
    begin 
     wait for 10 ns; 
     sTestIn <= (x"E", x"A7", "1"); 
     wait for 10 ns; 
     sTestIn <= (x"7", x"AC", "0"); 
     wait; 
    end process; 
end architecture sim; 

Answer 2

將數據從矢量（線性數組）轉換爲記錄的一種方法是通過使用聚合。

library ieee; 
use ieee.std_logic_1164.all; 

package TestPck is 
    subtype A is std_logic_vector (12 downto 9); 
    subtype B is std_logic_vector (8 downto 1); 
    subtype C is std_logic_vector (0 downto 0); 
    constant ABC_len: natural := A'length + B'length + C'length; 
    type tTest is record 
     A: std_logic_vector (A'RANGE); 
     B: std_logic_vector (B'RANGE); 
     C: std_logic_vector (C'RANGE); 
    end record tTest; 
    type tTests is array (natural range <>) of tTest; 
end package TestPck; 

library ieee; 
use ieee.std_logic_1164.all; 
use work.TestPck.all; 

entity tb is 
end entity tb; 

architecture sim of tb is 
    signal sTestIn:  tTest; 
    signal sMemWrData:  std_logic_vector(ABC_len - 1 downto 0); 
    signal sMemRdData:  std_logic_vector(ABC_len - 1 downto 0); 
    signal sTestOut:  tTest; 
    constant tests:  tTests (0 to 1) := 
      (0 => (x"E", x"A7", "1"), 1 => (x"7", x"AC", "0")); 
begin 
    sMemWrData <= sTestIn.A & sTestIn.B & sTestIn.C; 
    sMemRdData <= sMemWrData after 5 ns; 
    sTestOut <= 
     tTest'(sMemRdData(A'range), sMemRdData(B'range), SMemRdData(C'range)); 
process is 
    begin 
     wait for 10 ns; 
     sTestIn <= tests(0); 
     wait for 10 ns; 
     sTestIn <= tests(1); 
     wait for 10 ns; 
     wait; 
    end process; 
end architecture sim; 

合格表達集合體定義爲t檢驗記錄的與位置相關聯，其被分配給該記錄類型sTestOut的值。

這給出：

因此可以使用級聯用於組裝的矢量值（或在-2008的聚集體），並使用聚合爲合格的表達式來sMemRdData轉移到sTestOut。

如果您還沒有計劃宣佈的A，B或C亞型的對象，你可以聲明爲整數亞型：

library ieee; 
use ieee.std_logic_1164.all; 

package TestPck is 
    subtype A is natural range 12 downto 9; 
    subtype B is natural range 8 downto 1; 
    subtype C is natural range 0 downto 0; 
    constant ABC_len: natural := A'left + 1; 
    type tTest is record 
     A: std_logic_vector (A); 
     B: std_logic_vector (B); 
     C: std_logic_vector (C); 
    end record tTest; 
    type tTests is array (natural range <>) of tTest; 
end package TestPck; 

library ieee; 
use ieee.std_logic_1164.all; 
use work.TestPck.all; 

entity tb is 
end entity tb; 

architecture sim of tb is 
    signal sTestIn:  tTest; 
    signal sMemWrData:  std_logic_vector(ABC_len - 1 downto 0); 
    signal sMemRdData:  std_logic_vector(ABC_len - 1 downto 0); 
    signal sTestOut:  tTest; 
    constant tests:  tTests (0 to 1) := 
      (0 => (x"E", x"A7", "1"), 1 => (x"7", x"AC", "0")); 
begin 
    sMemWrData <= sTestIn.A & sTestIn.B & sTestIn.C; 
    sMemRdData <= sMemWrData after 5 ns; 
    sTestOut <= 
     tTest'(sMemRdData(A), sMemRdData(B), SMemRdData(C)); 
process is 
    begin 
     wait for 10 ns; 
     sTestIn <= tests(0); 
     wait for 10 ns; 
     sTestIn <= tests(1); 
     wait for 10 ns; 
     wait; 
    end process; 
end architecture sim; 

這可能是更容易一些閱讀。它會產生上面相同的波形。