intialze verilog中的二維數組

我想通過Xinlix軟件使用2維數組初始化內存。代碼在語法上是正確的，但是它的測試平臺給出了意想不到的輸出。intialze verilog中的二維數組

例如：

address 0:instruction=1081601; but required output=00108101

和

address 1:instruction=1048834; required output=00100102

誰能告訴我什麼是錯我的代碼？

module Imem (address, instruction); 
    input [31:0] address; 
    output  reg [31:0] instruction; 

    reg [31:0]sra [0:256];integer i; 

    // I-mem is read in every cycle. 
    // A read signal could be added if necessary. 
    always @(address) 
    begin 
    sra[32'h00000000]=32'h00108101; 
    sra[32'h00000001]=32'h00100102; 
    sra[32'h00000002]=32'h34100020; 
    sra[32'h00000003]=32'h38100020; 
    sra[32'h00000004]=32'h00108105; 
    sra[32'h00000005]=32'h00108106; 
    sra[32'h00000006]=32'h00108147; 
    sra[32'h00000007]=32'h00100148; 
    sra[32'h00000008]=32'h0010810F; 
    sra[32'h00000009]=32'h00108109; 
    sra[32'h0000000A]=32'h0010014A; 
    sra[32'h0000000B]=32'h0010810B; 
    sra[32'h0000000C]=32'h8C105555; 
    sra[32'h0000000D]=32'hAC10AAAA; 
    sra[32'h0000000E]=32'h31555555; 
    sra[32'h0000000F]=32'h28A00000; 
    sra[32'h00000010]=32'h00000000; 
    sra[32'h00000011]=32'h00000000; 

    for(i=32'd18;i<=32'd256;i=i+1) 
     sra[i]=32'h00000000; 

    instruction=sra[address]; 
    end 

endmodule

我的測試平臺是：

module instr_v_v; 

    // Inputs 
    reg [31:0] address; 

    // Outputs 
    wire [31:0] instruction; 

    // Instantiate the Unit Under Test (UUT) 
    Imem uut ( 
     .address(address), 
     .instruction(instruction) 
    ); 

    initial 
    begin 
     address=32'd0; 
     $display($time,"address=%h,instruction=%h",address,instruction); 
     // Initialize Inputs 


     // Wait 100 ns for global reset to finish 

     #10 address=32'd1; 
     #10 address=32'd2; 
     #10 address=32'd3; 
     #10 address=32'd4; 

     // Add stimulus here 
    end 

endmodule

來源

2014-06-06 user3715367

請分享你的測試平臺。我猜測有一個錯誤的基數，因爲1081601十進制是108101十六進制。或者它的代碼是一個調度問題。 – Greg

提供的測試臺沒有生成錯誤的檢查器。目前這個問題缺乏足夠的信息來診斷問題。 – Greg

我正在辛林ISE 8.2 version.Mr。格雷格你要求測試平臺，我已經分享了它，但現在你說這個問題缺乏足夠的信息。你想知道關於代碼的其他信息嗎？事實上，當我的代碼和代碼完好無損時，產生意想不到的輸 – user3715367

它看起來像它的正常工作，我改變了TB到低於你開車經過的每個解決您等待時間單位顯示該值。

波形：http://img42.com/8ED7S

這應該是輸出

   11address=00000000,instruction=00108101 
       22address=00000001,instruction=00100102 
       33address=00000002,instruction=34100020 
       44address=00000003,instruction=38100020 
       55address=00000004,instruction=00108105 



initial 
begin 
    #10 address=32'd0; 
    #1 $display($time,"address=%h,instruction=%h",address,instruction); 
    // Initialize Inputs 


    // Wait 100 ns for global reset to finish 

    #10 address=32'd1; 
     #1 $display($time,"address=%h,instruction=%h",address,instruction); 
    #10 address=32'd2; 
     #1 $display($time,"address=%h,instruction=%h",address,instruction); 
    #10 address=32'd3; 
     #1 $display($time,"address=%h,instruction=%h",address,instruction); 
    #10 address=32'd4; 
     #1 $display($time,"address=%h,instruction=%h",address,instruction); 

    // Add stimulus here 
end

來源

2014-06-10 04:15:30 user3719021

intialze verilog中的二維數組

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