使用for循環設計加法器vhdl

Question

我試圖通過實例化n位加法器的多個副本來使用/ generate循環來創建m位加法器。這是我迄今爲止的代碼，它不能通過給出錯誤來模擬： 「第44行：並非a_n的所有部分形式都是實際的」。 n位加法器被聲明爲組件，我已經成功地對它進行了測試，它的工作原理。 通過提供任何建議，要解決這個問題請幫助

entity m_bit_adder is 
generic (m : integer := 16; n : integer := 4); 
    Port (A_m : in STD_LOGIC_VECTOR (m-1 downto 0); 
      B_m : in STD_LOGIC_VECTOR (m-1 downto 0); 
      Cin_m : in STD_LOGIC; 
      Cout_m : out STD_LOGIC; 
      S_m : out STD_LOGIC_VECTOR (m-1 downto 0)); 
end m_bit_adder; 

architecture Behavioral of m_bit_adder is 

component n_bit_adder is 
generic (n_number : integer := 4); 
    Port (A_n : in STD_LOGIC_vector(n-1 downto 0); 
      B_n : in STD_LOGIC_vector(n-1 downto 0); 
      Cin_n : in STD_LOGIC; 
      S_n : out STD_LOGIC_vector(n-1 downto 0); 
      Cout_n : out STD_LOGIC); 
end component; 

signal sig_m : std_logic_vector (m downto 0); 


begin 

m_bit_adder : for j in 0 to m-1 generate 

n_bit : n_bit_adder generic map (n_number => n) 

port map ( 
        A_n(n-1) => A_m(j),  
       B_n(n-1)=> B_m(j), 
       S_n(n-1) => S_m(j), 
       Cin_n => sig_m(j), 
       Cout_n => sig_m(j+1)    
       ); 



end generate; 
sig_m(0) <= Cin_m; 
Cout_m <= sig_m(m); 

end Behavioral; 

這是我第n加法器代碼：

entity n_bit_adder is 
generic (n : integer := 4); 
    Port (A_n : in STD_LOGIC_vector(n-1 downto 0); 
      B_n : in STD_LOGIC_vector(n-1 downto 0); 
      Cin_n : in STD_LOGIC; 
      S_n : out STD_LOGIC_vector(n-1 downto 0); 
      Cout_n : out STD_LOGIC); 
end n_bit_adder; 
architecture Behavioral of n_bit_adder is 

component adder 
    Port (A : in STD_LOGIC; 
      B : in STD_LOGIC; 
      Cin : in STD_LOGIC; 
      S : out STD_LOGIC; 
      Cout : out STD_LOGIC); 

end component; 

signal sig_n : std_logic_vector (n downto 0); 


begin 

n_bit_adder : for i in 0 to n-1 generate 
one_bit : adder 

port map ( 
        A => A_n(i), 
       B => B_n(i), 
       S => S_n(i), 
       Cin => sig_n(i), 
       Cout => sig_n(i+1) 
       );    
end generate; 

sig_n(0) <= Cin_n; 
Cout_n <= sig_n(n); 

end Behavioral; 

Answer 1

的n_bit_adder使用正規側與A_n(n-1)中只有一個位被實例化：

n_bit : n_bit_adder generic map (n_number => n) 
    port map ( 
    A_n(n-1) => A_m(j),  
    .... 

但n_bit_adder組件具有作爲std_logic_vector爲A_n在多個位：

component n_bit_adder is 
    generic (n_number : integer := 4); 
    Port (A_n : in STD_LOGIC_vector(n-1 downto 0); 
    ... 

所以對於一個std_logic_vector(3 downto 0)然後A_n(2 downto 0)不使用的映射，這也是正式（左側）什麼錯誤消息「不是A_N的所有部分甲縮醛說有實際的「。

另請注意，它看起來像不同名稱n_number和n用於通用組件和端口上std_logic_vector長度。