每次我模擬下面的代碼時,我的輸出都是未定義的,我不知道爲什麼。我在代碼和模擬中都有數字庫。如果有人能幫助讓我知道。此外,在模擬輸入成爲00000..000而不是15和3未定義的輸出
模塊代碼的輸入:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
entity EXPONENT_FUNCTION is
Port (A : in STD_LOGIC_VECTOR (23 downto 0);
B : in STD_LOGIC_VECTOR (23 downto 0);
O : out STD_LOGIC_VECTOR (47 downto 0));
end EXPONENT_FUNCTION;
architecture Behavioral of EXPONENT_FUNCTION is
signal AIN, BIN, F : integer;
signal u : std_logic_vector (47 downto 0);
begin
AIN <= to_integer(signed (A));
BIN <= to_integer(signed (B));
F <= ((AIN)**(BIN));
u <= std_logic_vector(to_signed(F, 48));
O <= u;
end Behavioral;
模擬代碼:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY EXPONENT_TEST IS
END EXPONENT_TEST;
ARCHITECTURE behavior OF EXPONENT_TEST IS
COMPONENT EXPONENT_FUNCTION
PORT(
A : IN std_logic_vector(23 downto 0);
B : IN std_logic_vector(23 downto 0);
O : OUT std_logic_vector(47 downto 0)
);
END COMPONENT;
signal A : std_logic_vector(23 downto 0) := (others => '0');
signal B : std_logic_vector(23 downto 0) := (others => '0');
signal O : std_logic_vector(47 downto 0);
BEGIN
uut: EXPONENT_FUNCTION PORT MAP (
A => A,
B => B,
O => O
);
stim_proc: process
begin
A <= "000000000000000000001111";
B <= "000000000000000000000011";
wait for 100 ns;
wait;
end process;
END;
如果模擬自身上面的代碼,它的輸出將是不確定的,因爲不被驅動的輸入。您需要在您的問題中包含測試平臺的代碼。 (請參閱[MCVE](http://stackoverflow.com/help/mcve))。 –
我用模擬代碼 – Mrbeck101