VHDL編寫警告

1.8倍數位VHDL編寫警告

library IEEE; 
 
use IEEE.STD_LOGIC_1164.ALL; 
 
use ieee.std_logic_arith.all; 
 
use ieee.std_logic_unsigned.all; 
 

 
entity M8 is 
 
    Port (M1 : in STD_LOGIC_vector(7 downto 0); 
 
      M2 : in STD_LOGIC_vector(7 downto 0); 
 
      Mout : out STD_LOGIC_vector(15 downto 0) 
 
\t \t \t ); 
 
end M8; 
 
architecture Behavioral of M8 is 
 

 
begin 
 
process(M1,M2) 
 

 
variable A1: std_logic_vector(17 downto 0); 
 

 
begin 
 
A1(17 downto 0) := "0000000000" & M1(7 downto 0); 
 

 
for N in 1 to 9 loop 
 
if A1(0)='1' then 
 
A1(17 downto 9) := A1(17 downto 9) + '0'+ M2(7 downto 0); 
 
end if; 
 
A1(17 downto 0) := '0' & A1(17 downto 1); 
 
end loop; 
 
Mout<= A1(15 downto 0); 
 
end process; 
 

 
end Behavioral;

2.32位乘法器

library IEEE; 
 
use IEEE.STD_LOGIC_1164.ALL; 
 
use ieee.std_logic_arith.all; 
 
use ieee.std_logic_unsigned.all; 
 

 

 
entity M32 is 
 
    Port (M1 : in STD_LOGIC_vector(31 downto 0); 
 
      M2 : in STD_LOGIC_vector(31 downto 0); 
 
      Mout : out STD_LOGIC_vector(63 downto 0) 
 
\t \t \t ); 
 
end M32; 
 

 
architecture Behavioral of M32 is 
 

 
begin 
 
process(M1,M2) 
 

 
variable A1: std_logic_vector(65 downto 0); 
 

 
begin 
 
A1(65 downto 0) := "0000000000000000000000000000000000" & M1(31 downto 0); 
 

 

 
for N in 1 to 33 loop 
 
if A1(0)='1' then 
 
A1(65 downto 33) := A1(65 downto 33) + '0'+ M2(31 downto 0); 
 
end if; 
 
A1(65 downto 0) := '0' & A1(65 downto 1); 
 
end loop; 
 
Mout<= A1(63 downto 0); 
 
end process; 
 

 
end Behavioral;

library IEEE; 
 
use IEEE.STD_LOGIC_1164.ALL; 
 
use ieee.std_logic_arith.all; 
 
use ieee.std_logic_unsigned.all; 
 

 
entity MM32All is 
 

 
port(MMM1: in std_logic_vector(31 downto 0); 
 
     MMM2: in std_logic_vector(31 downto 0); 
 
\t \t MMMout: out std_logic_vector(63 downto 0) 
 
\t \t); 
 

 
end MM32All; 
 

 
architecture Behavioral of MM32All is 
 

 
component M32 port(MM1 : in std_logic_vector(31 downto 0); 
 
    MM2 : in std_logic_vector(7 downto 0); 
 
\t MMout:out std_logic_vector(39 downto 0) 
 
\t ); 
 
\t end component; 
 

 
signal MMb: std_logic_vector(31 downto 0); \t 
 
signal MMa: std_logic_vector(31 downto 0); 
 

 
signal MMo1: std_logic_vector(39 downto 0); 
 
signal MMo2: std_logic_vector(39 downto 0); 
 
signal MMo3: std_logic_vector(39 downto 0); 
 
signal MMo4: std_logic_vector(39 downto 0); 
 
signal MMout1: std_logic_vector(63 downto 0); 
 
begin 
 
Ma4: M32 port map (MM1=> MMb, MM2=> MMa(31 downto 24), MMout=> MMo4); 
 
Ma3: M32 port map (MM1=> MMb, MM2=> MMa(23 downto 16), MMout=> MMo3); 
 
Ma2: M32 port map (MM1=> MMb, MM2=> MMa(15 downto 8) , MMout=> MMo2); 
 
Ma1: M32 port map (MM1=> MMb, MM2=> MMa(7 downto 0) , MMout=> MMo1); 
 

 
MMout1 <= ("000000000000000000000000" & MMo1) + ("0000000000000000" & MMo2 & "00000000") 
 
+ ("00000000" & MMo3 & "0000000000000000") + (MMo4 & "000000000000000000000000"); 
 

 
MMb <= MMM1; 
 
MMa <= MMM2; 
 
MMMout <= MMout1; 
 
end Behavioral; 
 

 
library IEEE; 
 
use IEEE.STD_LOGIC_1164.ALL; 
 
use ieee.std_logic_arith.all; 
 
use ieee.std_logic_unsigned.all; 
 

 
entity M32 is 
 
port(MM1 : in std_logic_vector(31 downto 0); 
 
    MM2 : in std_logic_vector(7 downto 0); 
 
\t MMout:out std_logic_vector(39 downto 0) 
 
\t ); 
 
\t 
 
end M32; 
 

 
architecture Behavioral of M32 is 
 

 
component M8 Port (M1 : in STD_LOGIC_vector(7 downto 0); 
 
        M2 : in STD_LOGIC_vector(7 downto 0); 
 
        Mout : out STD_LOGIC_vector(15 downto 0) 
 
\t \t \t   ); 
 
\t \t \t \t \t \t end component; 
 
component M8b Port (M1 : in STD_LOGIC_vector(7 downto 0); 
 
        M2 : in STD_LOGIC_vector(7 downto 0); 
 
        Mout : out STD_LOGIC_vector(15 downto 0) 
 
\t \t \t   ); 
 
\t \t \t \t \t \t end component; 
 
component M8c Port (M1 : in STD_LOGIC_vector(7 downto 0); 
 
        M2 : in STD_LOGIC_vector(7 downto 0); 
 
        Mout : out STD_LOGIC_vector(15 downto 0) 
 
\t \t \t   ); 
 
        end component; 
 
component M8d Port (M1 : in STD_LOGIC_vector(7 downto 0); 
 
        M2 : in STD_LOGIC_vector(7 downto 0); 
 
        Mout : out STD_LOGIC_vector(15 downto 0) 
 
\t \t \t   ); 
 
        end component; \t \t \t \t \t \t 
 
signal internalMM1: std_logic_vector(31 downto 0); 
 
signal internalMM2: std_logic_vector(7 downto 0); 
 
signal internalMMout: std_logic_vector(39 downto 0); 
 
signal M8dout:std_logic_vector(15 downto 0); 
 
signal M8cout:std_logic_vector(15 downto 0); 
 
signal M8bout:std_logic_vector(15 downto 0); 
 
signal M8out:std_logic_vector(15 downto 0); 
 
begin 
 

 
--addres: for N in 0 to 3 generate 
 
FulMd32: M8d port map(M1=> internalMM1(31 downto 24), M2=> internalMM2, Mout=> M8dout); 
 
FulMb32: M8b port map(M1=> internalMM1(23 downto 16), M2=> internalMM2, Mout=> M8cout); 
 
FulMc32: M8c port map(M1=> internalMM1(15 downto 8), M2=> internalMM2, Mout=> M8bout); 
 
FulM32: M8 port map(M1=> internalMM1(7 downto 0), M2=> internalMM2, Mout=> M8out); 
 

 
internalMMout<=("000000000000000000000000" & M8out) 
 
    + ("0000000000000000" & M8bout & "00000000") + ("00000000" & M8cout & "0000000000000000") 
 
    + (M8dout & "000000000000000000000000"); 
 

 
internalMM1 <= MM1; 
 
internalMM2 <= MM2; 
 

 
MMout <= internalMMout; 
 
end Behavioral;

library IEEE; 
 
use IEEE.STD_LOGIC_1164.ALL; 
 
use IEEE.NUMERIC_STD.ALL; 
 
entity ALU is 
 
port(A :in std_logic_vector(31 downto 0); 
 
     B :in std_logic_vector(31 downto 0); 
 
\t \t SS:in std_logic_vector(2 downto 0); 
 
\t \t C :out std_logic_vector(63 downto 0); 
 
\t \t D :out std_logic_vector(31 downto 0); 
 
\t \t La,Sm,Eq: out std_logic); 
 
end ALU; 
 
architecture Behavioral of ALU is 
 
Component M32 is port (M1 : in STD_LOGIC_vector(31 downto 0); 
 
         M2 : in STD_LOGIC_vector(31 downto 0); 
 
         Mout : out STD_LOGIC_vector(63 downto 0)); 
 
end component; 
 

 
Component SUB32 is port(A : in STD_LOGIC_vector(31 downto 0); 
 
         B : in STD_LOGIC_vector(31 downto 0); 
 
         OFL:out std_logic; 
 
         S : out STD_LOGIC_vector(31 downto 0)); 
 
end component; 
 

 
Component adder32 is Port(A : in STD_LOGIC_vector(31 downto 0); 
 
          B : in STD_LOGIC_vector(31 downto 0); 
 
         Cin : in STD_LOGIC; 
 
         Cout : out STD_LOGIC; 
 
          S : out STD_LOGIC_vector(31 downto 0)); \t \t \t \t \t \t \t 
 
end component; 
 
signal aM1,aM2,bM1,bM2,cM1,cM2,cMout,bMout : STD_LOGIC_vector(31 downto 0); 
 
signal aMout: STD_LOGIC_vector(63 downto 0); 
 
signal Overflow: std_logic; 
 
       
 
begin 
 
A1: M32 port map(M1=> aM1, M2=>aM2, Mout=>aMout); 
 
A2: SUB32 port map(A=> bM1, B=> bM2, S=>bMout, OFL=>Overflow); 
 
A3: adder32 port map(A=> cM1, B=> cM2, Cout=>open,S=>cMout,Cin=>'0'); 
 

 
process(SS,A,B,Overflow,aMout,bMout,CMout) 
 
begin 
 
Case SS is 
 
When "000"=> aM1<=A; 
 
      aM2<=B; 
 
C<=aMout; 
 
When "001" => if Overflow='1' then 
 
       bM1<=A; 
 
       bM2<=B; 
 
\t D<=bMout; 
 
else 
 
    D<="00000000000000000000000000000000"; 
 
\t end if; 
 
when "010" => cM1<=A; 
 
       cM2<=B; 
 
\t D<= cMout; 
 
when "011" => if (A > B) then 
 
        La<='1'; 
 
\t Sm<='0'; 
 
\t Eq<='0'; 
 
       else if (A<B) then 
 
    \t    La<='0'; 
 
\t    Sm<='1'; 
 
\t     Eq<='0'; 
 
       else 
 
\t    La<='0'; 
 
\t    Sm<='0'; 
 
\t    Eq<='1'; 
 
\t \t \t end if; 
 
\t \t \t end if; 
 
\t when "100" => 
 
    \t  D <= (A and B); 
 
    \t when "101" => 
 
    \t  D <= (A or B); 
 
    \t when "110" => 
 
    \t  D <= (A xor B); \t \t \t \t \t 
 
When others=> C<="ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; 
 
       D<="ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; 
 
end case; 
 
end process; \t \t \t \t 
 
end Behavioral;

32位ALU

基於設備利用率摘要，乘法器的兩種設計具有非常相似的面積利用率。 8位乘法器的32位乘法器比單個32位乘法器多使用大約5％的邏輯單元。通過8位乘法器使用的32位乘法器的使用路徑數是單個32位乘法器的238％。即使使用不同的設計，他們的表現也是一樣的。

來源

2017-02-28 Yuan Cao

那麼，什麼是問題？另外，如果你想寫一個乘數，最簡單的方法是給你的操作數和結果類型「簽名」，然後簡單地寫'x <= a * b'。 –

使用代碼示例而不是Javascript/HTML/CSS代碼片段來包含您的VHDL代碼。你有具體的問題嗎？請參閱 [幫助中心]（http://stackoverflow.com/help），[我如何問一個好問題？]（http://stackoverflow.com/help/how-to-ask），[如何創建一個Minimal，Complete和Verifiable示例]（http://stackoverflow.com/help/mcve）並考慮參加[Tour]（http://stackoverflow.com/tour）。你的警告不足以證明。 – user1155120

scary_jeff表示您有很多模糊的乘法器方式。綜合工具很可能會對此感到困惑。

代替

use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all;

請有

use ieee.numeric_std.all;

代替

std_logic_vector(n-1 downto 0)

使用和

signed(n-1 downto 0);

然後你可以乘以*。

題外話，而是的

D<="00000000000000000000000000000000";

可以使用

D <= (others => '0');

來源

2017-03-01 15:32:12 FritzDC

回答

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