VHDL中的程序返回未知

Question

我必須比較功能代碼和rtl代碼。下面的代碼被寫爲一個16位輸入的二分量結構代碼。我試圖編寫以下電路：

在這裏，我所包圍的代碼和測試臺：

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 

entity two_s_complement_16bit_rtl is 
    Port (A : in STD_LOGIC_VECTOR (15 downto 0); 
      Cout : out STD_LOGIC_VECTOR (15 downto 0):= (others => '0')); 
end two_s_complement_16bit_rtl; 

architecture Behavioral of two_s_complement_16bit_rtl is 

procedure two_s_complement (
     A : in std_logic; 
     B : in std_logic; 
     C : out std_logic; 
     cout : out std_logic; 
     cin : in std_logic) is 

     begin 

     cout := ((not A) and B) xor (((not A) xor B) and cin); 

end procedure; 

begin 

    process (A) 
     variable temp_C, temp_Cout: STD_LOGIC_VECTOR(15 downto 0); 
     constant B_0 : STD_LOGIC := '1'; 
     constant B_1 : STD_LOGIC := '0'; 
     begin 

    for i in 0 to 15 loop 
      if (i = 0) then 
       two_s_complement (A(i), B_0 ,temp_C(i) ,temp_Cout(i) , B_1); 
      else 
       two_s_complement (A(i), B_1 ,temp_C(i) ,temp_Cout(i) , temp_C(i-1)); 
      end if; 

    end loop; 
    Cout <= temp_Cout; 
    end process; 

end Behavioral; 

的測試臺：

library IEEE; 
use IEEE.Std_logic_1164.all; 
use IEEE.Numeric_Std.all; 

entity two_s_complement_16bit_rtl_tb is 
end; 

architecture bench of two_s_complement_16bit_rtl_tb is 

    component two_s_complement_16bit_rtl 
     Port (A : in STD_LOGIC_VECTOR (15 downto 0); 
      Cout : out STD_LOGIC_VECTOR (15 downto 0):= (others => '0')); 
    end component; 

    signal A: STD_LOGIC_VECTOR (15 downto 0); 
    signal Cout: STD_LOGIC_VECTOR (15 downto 0):= (others => '0'); 

begin 

    uut: two_s_complement_16bit_rtl port map (A => A, 
              Cout => Cout); 

    stimulus: process 
    begin 


    -- Put initialisation code here 
    A <= "0100010010110000"; 
    wait for 10 ns; 

    A <= "0011000011110111"; 
    wait for 10 ns; 

    A <= "0000000000000001"; 
    wait for 10 ns; 

    A <= "0011110010110011"; 
    wait for 10 ns; 

    A <= "0010000100100001"; 
    wait for 10 ns; 

    A <= "0001011100100011"; 
    wait for 10 ns; 

    A <= "1011000110111001"; 
    wait for 10 ns; 

    A <= "0000001011001010"; 
    wait for 10 ns; 

    A <= "0011110110100000"; 
    wait for 10 ns; 

    A <= "0100000111111000"; 
    wait for 10 ns; 

    A <= "1011111001111100"; 
    wait for 10 ns; 

    A <= "1111000110000001"; 
    wait for 10 ns; 

    A <= "0111000111001011"; 
    wait for 10 ns; 

    A <= "1011011101101010"; 
    wait for 10 ns; 

    A <= "1111001001010111"; 
    wait for 10 ns; 



    -- Put test bench stimulus code here 
    wait; 
    end process; 


end; 

我已經考慮了第一個單元的三個輸入，但是其中的兩個Cin和B具有代碼中提到的恆定值，但是輸出是未知的。

Answer 1

有三個明顯的錯誤。

首先two_s_complement程序不分配Ç這是很容易解決：

procedure 
     two_s_complement (
      a:  in std_logic; 
      b:  in std_logic; 
      c:  out std_logic; 
      cout: out std_logic; 
      cin: in std_logic 
     ) is 
     variable inta: std_logic := not a; 
    begin 
     c := inta xor b xor cin; -- ADDED 
     cout := ((not a) and b) xor (((not a) xor b) and cin); 
     -- cout := (inta and b) or (inta and cin); 
    end procedure; 

這被示出爲與一個輸入反相的全加器。

其次，你得爲CIN的不正確關聯的過程調用：

 for i in 0 to 15 loop 
      if i = 0 then 
       two_s_complement ( 
        a => a(i), 
        b => b_0, 
        c => temp_c(i), 
        cout => temp_cout(i), 
        cin => b_1 
       ); 
      else 
       two_s_complement ( 
        a => a(i), 
        b => b_1, 
        c => temp_c(i), 
        cout => temp_cout(i), 
        cin => temp_cout(i - 1) -- WAS temp_c(i-1) 
       ); 
      end if; 

錯誤脫穎而出，當你使用命名關聯。

三two_s_complement_16bit_rtl的COUT輸出應該從temp_c分配：

 cout <= temp_c; -- WAS temp_cout; 

修復這三樣東西給：

一些看起來正確的。

這兩個補碼可以通過傳遞不是A到一個增量電路來簡化，所有不需要的門都是精簡的，並且消除B輸入。例如，您會發現LSB從不受影響。