信號<n1<1> _IBUF>是不完整的

Question

我想寫一個VHDL模塊，但我有一些輸入的問題，這裏是我的代碼：

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
--use ieee.std_logic_arith.all; 
use ieee.std_logic_signed.all; 


entity binary_add is 
    port(n1 : in std_logic_vector(3 downto 0); 
    n2 : in std_logic_vector(3 downto 0); 
    segments : out std_logic_vector(7 downto 0); 
    DNout : out std_logic_vector(3 downto 0)); 

end binary_add; 

architecture Behavioral of binary_add is 
begin 

DNout <= "1110"; 

process(n1, n2) 

variable x: integer; 


begin 

x:= conv_integer(n1(3)&n1(2)&n1(1)&n1(0)) + conv_integer(n2(3)&n2(2)&n2(1)&n2(0)); 

if(x = "0") then 

segments <= "10000001"; 

elsif(x = "1") then 

segments <= "11001111"; 

else 

segments <= "00000000"; 

end if; 

end process; 

end Behavioral; 

我得到這些錯誤：

WARNING:PhysDesignRules:367 - The signal <n1<1>_IBUF> is incomplete. The signal 
    does not drive any load pins in the design. 
WARNING:PhysDesignRules:367 - The signal <n1<2>_IBUF> is incomplete. The signal 
    does not drive any load pins in the design. 
WARNING:PhysDesignRules:367 - The signal <n1<3>_IBUF> is incomplete. The signal 
    does not drive any load pins in the design. 
WARNING:PhysDesignRules:367 - The signal <n2<1>_IBUF> is incomplete. The signal 
    does not drive any load pins in the design. 
WARNING:PhysDesignRules:367 - The signal <n2<2>_IBUF> is incomplete. The signal 
    does not drive any load pins in the design. 
WARNING:PhysDesignRules:367 - The signal <n2<3>_IBUF> is incomplete. The signal 
    does not drive any load pins in the design. 
WARNING:Par:288 - The signal n1<1>_IBUF has no load. PAR will not attempt to route this signal. 
WARNING:Par:288 - The signal n1<2>_IBUF has no load. PAR will not attempt to route this signal. 
WARNING:Par:288 - The signal n1<3>_IBUF has no load. PAR will not attempt to route this signal. 
WARNING:Par:288 - The signal n2<1>_IBUF has no load. PAR will not attempt to route this signal. 
WARNING:Par:288 - The signal n2<2>_IBUF has no load. PAR will not attempt to route this signal. 
WARNING:Par:288 - The signal n2<3>_IBUF has no load. PAR will not attempt to route this signal. 
WARNING:Par:283 - There are 6 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. 

錯誤似乎很複雜，但實際上它說，我認爲，無法路由我的n1和n2信號的其他3個輸入。我不明白爲什麼會發生這種情況，但我只想將n1和n2帶符號的數字總和顯示爲7段顯示。如果有人能幫我弄清楚這個問題，我會很感激。

Answer 1

第一：不要使用std_logic_arith或std_logic_signed - 我已經written about why not。第二：你已經創建了一個異步進程，這在FPGA中是非常好的練習，這些練習是以同步的方式使用（以及工具希望你使用的）。創建一個時鐘輸入並使用它。你可以異步，但直到你真的知道你在做什麼，避免它。一旦你真的知道你在做什麼，你可能會避免它，因爲你知道它會是多麼討厭:)

我會讓我的端口signed類型和use ieee.numeric_stdd.all;。甚至在輸入端口上使用integer類型。如果這是頂級塊，你需要把一個包裝周圍採取的最引腳std_logic_vectors，把它們變成整數，並將它們送入你上面寫的塊：

n1 <= to_integer(signed(n1_pins)); 

然後你需要做這樣的事情...

architecture Behavioral of binary_add is 
begin 
DNout <= "1110"; 
process(clk) 
    variable x: integer; 
begin 
    x:= n1+n2; 
    case x 
    when 0 => segments <= "10000001"; 
    when 1 => segments <= "11001111"; 

等

或者創建一個常量數組整數轉換成7段，做

segments <= int_to_7seg(x);