在Nexys4 DDR板上使用Verilog執行FIFO

Question

Simulation output

你好，請幫我解決這個問題。 ..with代碼如下buff_mem.v

一切工作正常，直到模擬，但問題出現時，我試圖在板上編程（Nexys4 DDR）。當我想寫入數據直到其深度爲止（即直到fifo_counter = f）時，只需一次按下一個彈出窗口即可顯示滿的空標誌。 我想寫入多個數據直到其深度（全部），然後讀取直到其空。 ..沒有發生。是按按鈕多次寫入和閱讀'按一下或什麼我不知道的問題？ PLIZ幫助我的代碼！

`define BUF_WIDTH 4  
`define BUF_SIZE (1<<`BUF_WIDTH) 
module buff_mem(clk, rst, wr_en, rd_en, buf_in, buf_out, buf_empty, buf_full, fifo_counter); 
input     rst, clk, wr_en, rd_en; 
input [7:0]   buf_in;     
output[7:0]   buf_out;     
output    buf_empty, buf_full;  
output[(`BUF_WIDTH - 1):0] fifo_counter;    

reg[7:0]    buf_out; 
reg     buf_empty, buf_full; 
reg[(`BUF_WIDTH - 1):0] fifo_counter; 
reg[(`BUF_WIDTH - 1):0] rd_ptr, wr_ptr;  // pointer to read and write addresses 
reg[7:0] buf_mem [`BUF_SIZE - 1 : 0];   // RAM 
always @(fifo_counter) 
begin 
    buf_empty = (fifo_counter==0); 
    buf_full = (fifo_counter==(`BUF_SIZE - 1)); 
end 

always @(posedge clk or posedge rst) 
begin 
    if(rst) 
     fifo_counter <= 0; 
    else if((!buf_full && wr_en) && (!buf_empty && rd_en)) 
     fifo_counter <= fifo_counter; 
    else if(!buf_full && wr_en) 
     fifo_counter <= fifo_counter + 1; 
    else if(!buf_empty && rd_en) 
     fifo_counter <= fifo_counter - 1; 
    else 
     fifo_counter <= fifo_counter; 
end 

always @(posedge clk or posedge rst)  //read 
begin 
    if(rst) 
     buf_out <= 0; 
    else 
    begin 
     if(rd_en && !buf_empty) 
     buf_out <= buf_mem[rd_ptr]; 
     else 
     buf_out <= buf_out; 
    end 
end 

always @(posedge clk)     //write 
begin 
    if(wr_en && !buf_full) 
     buf_mem[ wr_ptr ] <= buf_in; 
    else 
     buf_mem[ wr_ptr ] <= buf_mem[ wr_ptr ]; 
end 

always@(posedge clk or posedge rst)  //handling rd_ptr & wr_ptr 
begin 
    if(rst) 
    begin 
     wr_ptr <= 0; 
     rd_ptr <= 0; 
    end 
    else 
    begin 
     if(!buf_full && wr_en) wr_ptr <= wr_ptr + 1; 
     else wr_ptr <= wr_ptr; 
     if(!buf_empty && rd_en) rd_ptr <= rd_ptr + 1; 
     else rd_ptr <= rd_ptr; 
    end 
end 
endmodule 

這裏的約束文件吧 -

## Clock signal 
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz 

##Switches 
set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { wr_en }]; #IO_L24N_T3_RS0_15 Sch=sw[0] 
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { rd_en }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] 
set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { buf_in[0] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] 
set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { buf_in[1] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] 
set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { buf_in[2] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] 
set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { buf_in[3] }]; #IO_L7N_T1_D10_14 Sch=sw[5] 
set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { buf_in[4] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] 
set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { buf_in[5] }]; #IO_L5N_T0_D07_14 Sch=sw[7] 
set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { buf_in[6] }]; #IO_L24N_T3_34 Sch=sw[8] 
set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { buf_in[7] }]; #IO_25_34 Sch=sw[9] 

## LEDs 
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { buf_empty }]; #IO_L18P_T2_A24_15 Sch=led[0] 
set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { buf_full }]; #IO_L24P_T3_RS1_15 Sch=led[1] 
set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { buf_out[0] }]; #IO_L17N_T2_A25_15 Sch=led[2] 
set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { buf_out[1] }]; #IO_L8P_T1_D11_14 Sch=led[3] 
set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { buf_out[2] }]; #IO_L7P_T1_D09_14 Sch=led[4] 
set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { buf_out[3] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] 
set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { buf_out[4] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] 
set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { buf_out[5] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] 
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { buf_out[6] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] 
set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { buf_out[7] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] 

##Buttons 
set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { rst }]; #IO_L9P_T1_DQS_14 Sch=btnc 
set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { wr_en }]; #IO_L4N_T0_D05_14 Sch=btnu 
set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { rd_en }]; #IO_L12P_T1_MRCC_14 Sch=btnl 

Answer 1

的按鈕需要一個去抖電路。 Here是Verilog中的一個例子，但是我自己並沒有嘗試過。每個按鈕應該有一個此模塊的實例（例如wr_en，rd_en）。

要查看按下按鈕時發生了什麼，fifo_counter也可能連接到LED。據我所見，從board schematic，有可用的指示燈。

LED10 -> U14 
LED13 -> V14 
LED14 -> V12 
LED15 -> V11