Vhdl錯誤，我不明白

Question

我有一個問題，我的VHDL代碼。在active-hdl中它可以很好地工作，但是當我嘗試在使用ise設計xilinx的FPGA電路板上實現它時，我遇到了一個組件的問題。我發現該錯誤是：

ERROR:Xst:827 - "E:/proiect_final/dispozitiv_impartitor/src/generator_square_wave.vhd" line 16: Signal numar_intermediar<0> cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 

entity generator_square_wave is 
    port(clock,reset :in bit; 
     controler:std_logic_vector(2 downto 0); 
     numar:out std_logic_vector(7 downto 0); 
     data_clock:out bit); 
end generator_square_wave ; 

architecture descriere of generator_square_wave is 
signal reset1:std_logic; 
begin 
     process (clock,reset) -- here it shows me the error 
     variable numar_intermediar:bit_vector(3 downto 0):="0000"; 
    variable numar_intermediar2:std_logic_vector(3 downto 0); 
    variable bitul:bit; 
    begin 
     reset1<=to_stdulogic(reset); 
      if rising_edge(reset1) then 
       numar_intermediar:="0001"; 
      numar_intermediar2:=To_StdLogicVector(numar_intermediar); 
      numar(0)<=numar_intermediar2(0); 
      numar(1)<=numar_intermediar2(1); 
      numar(2)<=numar_intermediar2(2); 
      numar(3)<=numar_intermediar2(3); 
      numar(4)<='0'; 
      numar(5)<='0'; 
      numar(6)<='0'; 
      numar(7)<='0'; 

     else if(clock'event and clock ='1' and controler="001")then 
       bitul:=numar_intermediar(0); 
      numar_intermediar:=numar_intermediar srl 1; 
      numar_intermediar(3):=bitul; 
      numar_intermediar2:=To_StdLogicVector(numar_intermediar); 
      numar(0)<=numar_intermediar2(0); 
      numar(1)<=numar_intermediar2(1); 
      numar(2)<=numar_intermediar2(2); 
      numar(3)<=numar_intermediar2(3); 
      numar(4)<='0'; 
      numar(5)<='0'; 
      numar(6)<='0'; 
      numar(7)<='0'; 
     if(reset/='1' and controler/="001")then 
      numar<="00000000"; 
     end if; 
    end if; 
    end if; 
      data_clock<=clock; 
     end process; 
end descriere; 

Answer 1

你有幾個問題。首先，您不應將復位視爲時鐘（即使用rising_edge()）。如果它是異步的，你應該這樣寫：

if reset1 = '1' then 
    ... 

下面這行也有問題（不知道這是嚴格非法的，但它不推薦）：

if(clock'event and clock ='1' and controler="001")then 

這應該是：

if clock'event and clock = '1' then 
    if controler = "001" then 

（用另外的end if相匹配。）

即SHO至少允許它合成。

您可能還想聲明reset1<=to_stdulogic(reset)而不是將其包含在過程中，並且還可以進行其他可能的更改，但它們並不重要（除非我錯過了某些內容）。