沒有這16位超前進加法器看起來在本月結構的Verilog是否正確？

Question

我完成了這個16位進位向前加法器，問教授這​​是否正確。他告訴我它錯了。我要求就得到了如何建立使用結構Verilog的一個想法幫助。有人可以幫我驗證我的代碼有什麼問題嗎？

  `timescale 1ns/1ns 
      module fulladder(a, b, c, s, cout); //one bit fulladder 

        //the wires 
       wire w1, w2, w3, w4, s, cout; 

       input a, b, c; 
       output s, cout; 
       reg [0 : 0] s,cout; //register with one bit 

       //exclusive or gate with 1 ns delay 
        xor #1 
        g1(w1, a, b), 
        g2(s, w1, c); 
       //and gate with 1 ns delay 
        and #1 
        g3(w2, c, b), 
        g4(w3, c, a), 
        g5(w4, a, b); 
        //or gate with 1 ns delay 
        or #1 
        g6(cout, w2, w3, w4); 

       endmodule 

      //16bit carry look ahead 
      module sixteen_bit_carry_lookahead(a, b, c, s, cout); 
       input [15:0] a, 
       input [15:0] b, 
       input  c, //Carry in 
       output [15:0] s, //Sum 
       output  cout //Carry 

      //wires 
      wire [3:1] carry, [3:0] p, [3:0] g, [3:1] carry; 
      fulladder f0(.a(a[0]), .b(b[0]), .c(c),.s(s[0]),.cout(),.g(g[0]),.p([0])); 
      fulladder f1(.a(a[1]),.b(b[1]),.c(carry[1]),.s(s[1]),.cout(),.g(g[1]),.p([1])); 
      fulladder f2(.a(a[2]), .b(b[2]), .c(carry[2]), .s(s[2]), .cout(), .g(g[2]),.p([2])); 
      fulladder f3(.a(a[3]), .b(b[3]), .c(carry[3]), .s(s[3]), .cout(), .g(g[3]), .p([3])); 
      fulladder f4(.a(a[4]), .b(b[4]), .c(carry[4]), .s(s[4]), .cout(), .g(g[4]), .p([4])); 
      fulladder f5(.a(a[5]), .b(b[5]), .c(carry[5]), .s(s[5]), .cout(), .g(g[5]), .p([5])); 
      fulladder f6(.a(a[6]), .b(b[6]), .c(carry[6]), .s(s[6]), .cout(), .g(g[6]), .p([6])); 
      fulladder f7(.a(a[7]), .b(b[7]), .c(carry[7]), .s(s[7]), .cout(), .g(g[7]), .p([7])); 
      fulladder f8(.a(a[8]), .b(b[8]), .c(carry[8]), .s(s[8]), .cout(), .g(g[8]), .p([8])); 
      fulladder f9(.a(a[9]), .b(b[9]), .c(carry[9]), .s(s[9]), .cout(), .g(g[9]), .p([9])); 
       . 
       . //goes all the way to 16 bit 
       . 
      fulladder f15(.a(a[15]),.b(b[15]),.c(carry[15]),.s(s[15]),.cout(),.g(g[15),.p([15])); 

      endmodule 

      //the carry look ahead adder with inputs and outputs 
      module carry_lookahead(.p, .g, .c, .cout); 
       input .p(p); //input [15:0] 
       input .g(g); //input [15:0] 
       output .c(carry); //output [15:1] 
       output .cout (cout); //output 

      endmodule 

Answer 1

你已經包括不具有繁殖p並生成您在實例迷上了g輸出的fulladder。我會創建一個名爲propagate_adder與這些輸出新的模塊，並刪除生成cout的邏輯。

模塊sixteen_bit_carry_lookahead缺少實例carry_lookahead，這是進位路徑所必需的。

在fulladder的聲明中，您有reg [0:0]，這與編寫reg相同。