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我需要一個Makefile來編譯當前目錄下的所有東西,並遞歸下去,最好使用編譯器的依賴關係(-M等),這樣每當我鍵入「make」時,儘可能少地重新編譯。大型C++項目的Makefile模板?
此外,爲什麼這不是Makefile文檔的第1頁?
我需要一個Makefile來編譯當前目錄下的所有東西,並遞歸下去,最好使用編譯器的依賴關係(-M等),這樣每當我鍵入「make」時,儘可能少地重新編譯。大型C++項目的Makefile模板?
此外,爲什麼這不是Makefile文檔的第1頁?
雖然我會建議使用像cmake或類似的工具,但我知道有時使用普通的舊Makefile會更容易或更好。
下面是我的一些項目中使用的一個Makefile文件,它會創建使用gcc依賴性的文件:
# Project Name (executable)
PROJECT = demoproject
# Compiler
CC = g++
# Run Options
COMMANDLINE_OPTIONS = /dev/ttyS0
# Compiler options during compilation
COMPILE_OPTIONS = -ansi -pedantic -Wall
#Header include directories
HEADERS =
#Libraries for linking
LIBS =
# Dependency options
DEPENDENCY_OPTIONS = -MM
#-- Do not edit below this line --
# Subdirs to search for additional source files
SUBDIRS := $(shell ls -F | grep "\/")
DIRS := ./ $(SUBDIRS)
SOURCE_FILES := $(foreach d, $(DIRS), $(wildcard $(d)*.cpp))
# Create an object file of every cpp file
OBJECTS = $(patsubst %.cpp, %.o, $(SOURCE_FILES))
# Dependencies
DEPENDENCIES = $(patsubst %.cpp, %.d, $(SOURCE_FILES))
# Create .d files
%.d: %.cpp
$(CC) $(DEPENDENCY_OPTIONS) $< -MT "$*.o $*.d" -MF $*.d
# Make $(PROJECT) the default target
all: $(DEPENDENCIES) $(PROJECT)
$(PROJECT): $(OBJECTS)
$(CC) -o $(PROJECT) $(OBJECTS) $(LIBS)
# Include dependencies (if there are any)
ifneq "$(strip $(DEPENDENCIES))" ""
include $(DEPENDENCIES)
endif
# Compile every cpp file to an object
%.o: %.cpp
$(CC) -c $(COMPILE_OPTIONS) -o [email protected] $< $(HEADERS)
# Build & Run Project
run: $(PROJECT)
./$(PROJECT) $(COMMANDLINE_OPTIONS)
# Clean & Debug
.PHONY: makefile-debug
makefile-debug:
.PHONY: clean
clean:
rm -f $(PROJECT) $(OBJECTS)
.PHONY: depclean
depclean:
rm -f $(DEPENDENCIES)
clean-all: clean depclean
尼斯。我在include之前放了一個(並將縮進更改爲製表符)以使其工作。 – 2013-02-14 21:39:54