-2
這個結構計數器必須按這種方式計算： 0 ... 9 0 ... 9 0..3再次... 我認爲我的問題是在最後的懸浮，在gtk波我有問題只與counter2！我不知道爲什麼，請幫助...這個vhdl代碼有什麼問題？
circuit.. http://www.cromo-pharma.it/circuito.jpg
---------component instantiations-----------
signal sR2, sE2, sR1 : std_logic;
signal s2, s3, s8 : std_logic;
signal s0sec, s1sec, s2sec : std_logic;
signal c1out, c2out : std_logic_vector (3 downto 0);
signal dec1out, dec2out : std_logic_vector(15 downto 0);
begin
i2: counter1 port map (clk => clk, reset => sR1, count1 => c1out);
i3: counter2 port map (clk => clk, reset => sR2, en2 => sE2, count2 => c2out);
i5: deco port map (binary_in => c1out, decoder_out => dec1out);
i6: deco port map (binary_in => c2out, decoder_out => dec2out);
sR1 <= ((s8 and (s0sec or s1sec)) or (s2sec and s2)) or reset;
sR2 <= (s2 and s2sec);
sE2 <= s8;
s2 <= dec1out(2); --_a _b c _d 0010
s3 <= dec1out(3); --_a _b c d 0011
s8 <= dec1out(8); -- a _b _c _d 1000
s0sec <= dec2out(0); -- _a _b _c _d 0000
s1sec <= dec2out(1); -- _a _b _c d 0001
s2sec <= dec2out(2); -- _a _b c _d 0010
i4: data_out <= c1out;
---------------end----------------
--decoder--
architecture dec of deco is
begin
decoder_out <= "1000000000000000" when binary_in="1111" else
"0100000000000000" when binary_in="1110" else
"0010000000000000" when binary_in="1101" else
"0001000000000000" when binary_in="1100" else
"0000100000000000" when binary_in="1011" else
"0000010000000000" when binary_in="1010" else
"0000001000000000" when binary_in="1001" else
"0000000100000000" when binary_in="1000" else
"0000000010000000" when binary_in="0111" else
"0000000001000000" when binary_in="0110" else
"0000000000100000" when binary_in="0101" else
"0000000000010000" when binary_in="0100" else
"0000000000001000" when binary_in="0011" else
"0000000000000100" when binary_in="0010" else
"0000000000000010" when binary_in="0001" else
"0000000000000001" when binary_in="0000" else
"XXXXXXXXXXXXXXXX";
end architecture dec;
--counter with enable--
entity counter2 is
port ( clk : in std_logic;
reset : in std_logic;
count2 : out std_logic_vector (3 downto 0);
en2 : in std_logic
);
end entity counter2;
architecture RTL of counter2 is
begin
process (clk, reset, en2) is -- processo di verifica
variable cnt : unsigned(3 downto 0);
begin
if reset = '1' then cnt := (others => '0');
elsif rising_edge(clk) and en2='1' then
if en2 = '1' then cnt := cnt + 1;
end if;
end if;
count2 <= std_logic_vector(cnt);
end process;
--standard counter--
entity counter1 is
port ( clk : in std_logic;
reset : in std_logic;
count1 : out std_logic_vector (3 downto 0)
);
end entity counter1;
architecture RTL of counter1 is
begin
process (clk, reset) is -- processo di verifica
variable cnt : unsigned(3 downto 0);
begin
if reset = '1' then cnt := (others => '0');
elsif rising_edge(clk) then cnt := cnt + 1;
end if;
count1 <= std_logic_vector(cnt);
end process;
當你分配sR1，sR2，sE2時，你是否檢查過表達式？它們不是顯而易見的，所以你可能想添加一些註釋（或者編寫更簡單的代碼）。 – Philippe 2012-01-17 18:39:00
問題是什麼？你看到哪些行爲不正確？你能發表一些波形圖或信號值序列，並指出應有哪些不同？ – 2012-01-18 13:50:53
@MartinThompson嗨！謝謝回答。關於counter1的每個連接都很好（除了R1信號）。關於counter2的每個連接都會在gtkwave中返回一個紅色值（「U」）。我不明白爲什麼。如果這沒有幫助，我會從波形中放置一個屏幕！謝謝。 – 2012-01-18 16:24:03