如何：多維數組vhdl

Question

我想創建一個VHDL 5維數組，但我不確定如何設置和初始化位。

這裏是我到目前爲止有：

type \1-line\ is array (4 - 1 downto 0) of unsigned (32 - 1 downto 0); 
    type square is array (4 - 1 downto 0) of \1-line\; 
    type cube is array (4 - 1 downto 0) of square; 
    type hypercube is array (4 - 1 downto 0) of cube; 
    type \5-cube\ is array (4 - 1 downto 0) of cube; 

    signal mega_array : \5-cube\; 
    begin 
     process (clock, reset) begin 
       if (reset == '1') then 
         mega_array <= '0'; 
       end if; 
     end process; 
    end behv; 

Answer 1

一個辦法做到這一點是與 '（別人=>' 0 '）'。這是將矢量的所有位設置爲'0'的乾淨安全的方法。您必須爲陣列的每一層執行此操作。

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all; 

entity test is 
    port (
     clock : in std_logic; 
     reset : in std_logic); 
end entity test; 

architecture behv of test is 

    type \1-line\ is array (4 - 1 downto 0) of unsigned (32 - 1 downto 0); 
    type square is array (4 - 1 downto 0) of \1-line\; 
    type cube is array (4 - 1 downto 0) of square; 
    type \5-cube\ is array (4 - 1 downto 0) of cube; 

    signal mega_array : \5-cube\; 

begin 

    process (clock, reset) 
    begin 
     if (reset = '1') then   -- note: not '==' 
      mega_array <= (others => (others => (others => (others => (others => '0'))))); 
     end if; 
    end process; 

end architecture behv; 

注意的是，雖然\1-...命名是正確的VHDL，我不會用它來避免討厭的工具的問題。我不確定他們會來，但避免他們會更好，然後解決它們。我會用t_1line來代替。

Answer 2

聚集是你需要什麼：

(others => '0')套在載體中的所有位爲「0」

(others => (others => '0'))矢量集的陣列的所有元素的所有位「0」

(others => (others => (others => '0'))) ...等等:)