不支持子程序中的信號參數錯誤

Question

我的代碼是關於使用VHDL和maxplus2的乒乓遊戲。我無法得到它的遵守。

library ieee; 
use ieee.std_logic_1164.all; 
-- use ieee.std_logic_unsigned.all; 
-- use ieee.std_logic_arith.all; 

entity center is 
    port ( 
     clk: in std_logic; 
     ca:  in std_logic; 
     cb:  in std_logic; 
     enable: in std_logic; 
     a:  in std_logic; 
     b:  in std_logic; 
     ball: out std_logic_vector(16 downto 0); 
     sa:  out std_ulogic; 
     sb:  out std_ulogic; 
     over: inout std_ulogic 
    ); 
end center; 

architecture behavior of center is 
    signal direction : integer range 0 to 2; 
    signal num : integer range -1 to 17; 
begin 
    process (enable,ca,cb,a,b,clk) 
    begin   
     if enable = '0' then 
      over <= '0'; 
      sa <= '0'; 
      sb <= '0'; 
     elsif enable = '1' and rising_edge(clk) then 
      if direction = 2 then 
       if ca = '1' then 
        direction <= 0;  
        num <= 1; 
       elsif cb = '1' then 
        direction <= 1; 
        num <= 16; 
       else 
        direction <= 2; 
        num <= 8; 
       end if; 
      elsif direction = 0 and num > 0 then 
       if b = '1' then 
        if num < 2 then 
         num <= num - 1; 
         direction <= 1; 
        else 
         direction <= 2; 
         sa <= '1' after 10 ns; 
         sb <= '0' after 10 ns; 
         over <= not over after 10 ns; 
        end if; 
       end if;   
      elsif direction = 1 and num <= 16 then 
       if a = '1' then 
        if num >= 14 then 
         num <= num + 1; 
         direction <= 2; 
        else 
         direction <= 2; 
         sa <= '0' after 10 ns; 
         sb <= '1' after 10 ns; 
         over <= not over after 10 ns; 
        end if; 
       end if; 
      elsif direction = 0 and num = -1 then 
       num <= 8; 
       direction <= 2; 
       sa <= '0' after 10 ns; 
       sb <= '1' after 10 ns; 
       over <= not over after 10 ns; 
      elsif direction = 0 and num = -1 then 
       num <= 8; 
       direction <= 2; 
       sa <= '0' after 10 ns; 
       sb <= '1' after 10 ns; 
       over <= not over after 10 ns; 
      end if; 
     end if; 
    end process; 
end architecture behavior; 

但我得到一個錯誤：

signal parameter in a subprogram is not supported

我很困惑，我不知道爲什麼我得到這個錯誤。

Answer 1

我想大衛也說你需要提供更多的信息。 對我來說，看起來像是你正在寫一個測試平臺，上面的代碼不能被正確合成。 ISE會告訴你，你的語法正常，但延遲被忽略IE after關鍵字。 after關鍵字僅用於模擬。

這就是說，我還會清理代碼中有很多冗餘。 FX
最後兩條elsif聲明。只需要一個。和敏感列表。只有clk和enable應該在那裏。

我試圖清理代碼：

process (enable,clk) 
begin   
    if enable = '0' then 
     over <= '0'; 
     sa <= '0'; 
     sb <= '0'; 
    elsif rising_edge(clk) then 
     case(direction) is 

      when 0 => 
       if num > 0 then 
        if b = '1' then 
         if num < 2 then 
          num <= num - 1; 
          direction <= 1; 
         else 
          direction <= 2; 
          sa <= '1' after 10 ns; 
          sb <= '0' after 10 ns; 
          over <= not over after 10 ns; 
         end if; 
        end if; 
       elsif num = -1 then 
        num <= 8; 
        direction <= 2; 
        sa <= '0' after 10 ns; 
        sb <= '1' after 10 ns; 
        over <= not over after 10 ns;        
       end if;     
      when 1 => 
       if num <= 16 then 
        if a = '1' then 
         if num >= 14 then 
          num <= num + 1; 
          direction <= 2; 
         else 
          direction <= 2; 
          sa <= '0' after 10 ns; 
          sb <= '1' after 10 ns; 
          over <= not over after 10 ns; 
         end if; 
        end if;     
       end if;     
      when 2 => 
       if ca = '1' then 
        direction <= 0;  
        num <= 1; 
       elsif cb = '1' then 
        direction <= 1; 
        num <= 16; 
       else 
        direction <= 2; 
        num <= 8; 
       end if; 
      when others => NULL; 

     end case ; 
    end if; 
end process; 

嘗試並刪除after關鍵字，看看它是否會編譯即可。