減去std_logic_vector我減去從整數STD_LOGIC_VECTOR問題。從整數
這是我現在所擁有的代碼:
entity ROM is
Port ( hcount: in STD_LOGIC_VECTOR(9 downto 0);
vcount: in STD_LOGIC_VECTOR(9 downto 0);
hpos: in integer;
vpos: in integer;
clk25: in STD_LOGIC;
Pixeldata: out std_logic);
end ROM;
architecture Behavioral of ROM is
signal romtemp : std_logic_vector(9 downto 0);
shared variable yas : integer range 0 to 9 := 0;
shared variable xas : integer range 0 to 9 := 0;
Type RomType is array (9 downto 0) of std_logic_vector(9 downto 0);
Constant Rom: RomType :=
("0001111000", "0111111110", "0111111110", "1111111111", "1111111111"
, "1111111111", "1111111111", "0111111110", "0111111110", "0001111000");
begin
process(clk25)
begin
if(hpos > hcount - 10) and (hpos <= hcount) and (vpos > vcount - 10) and (vpos <= vcount) then
xas := hpos - to_integer(unsigned(hcount));
end if;
end process;
end Behavioral;
的問題是下面一行代碼:
xas := hpos - to_integer(unsigned(hcount));
我試圖把在整數名爲XAS減法。該行發生
以下錯誤:
Error: Multiple declarations of unsigned included via multiple use clauses; none are made directly visible
Error: Expecting type unsigned for < unsigned(hcount) >.
Error: Formal < arg > has no actual or default value.
Error: Type integer is not an array type and cannot be indexed
Error: found '0' definitions of operator "=", cannot determine exact overload matching definition for "-"
有人可以幫助我這個錯誤? (我在VHDL初學者)
最後一項非常重要。儘量不要使用共享變量,除非你知道你在做什麼。在流程範圍中使用變量,或者在體系結構範圍內使用信號。如果這不符合你想要達到的目標,那麼我希望你來自不同的編程語言。 VHDL是一種硬件設計語言:代碼中可能存在很多,但最終還是需要將其視爲寄存器和邏輯。並非一切都可能存在,例如零傳播延遲。 – JHBonarius