使用帶端口映射的去抖動設計FSM的VHDL

Question

我使用VHDL創建了我的FSM，現在我想使用端口映射去抖動代碼。 雖然我與協會有困難。事實上，我想在驅動FSM的信號中插入debouncebutton組件。

entity myFSM is 
    Port (CLK : in STD_LOGIC; 
      RST : in STD_LOGIC; 
      IN0 : in STD_LOGIC; 
      IN1 : in STD_LOGIC; 
      IN2 : in STD_LOGIC; 
      LED : out STD_LOGIC_VECTOR (7 downto 0)); 
end myFSM; 

architecture Behavioral of myFSM is 
     type state is (A, B, C); 
     signal currentS, nextS: state; 

     component debouncebutton 
      Port (clk  : in std_logic;  -- connect it to the Clock of the board 
      rst  : in std_logic;  -- connect it to the Reset Button of the board   
      input : in std_logic;  -- connect it to the Push Button of the board 
      output : out std_logic  -- connect it to your circuit 
     ); 
     end component; 
begin 
myFSM_comb: process (currentS, IN0, IN1, IN2) 
begin 
    case currentS is 
     when A => LED <= "11111111"; 
         if IN0 = '1' then nextS<=B; 
         elsif IN1 = '1' then nextS<=C; 
         else   nextS<=A; 
         end if; 
     when B => LED <= "11000011"; 
         if IN0 = '1' then nextS<=C; 
         elsif IN1 = '1' then nextS<=A; 
         else nextS<=B; 
         end if; 
     when C => LED <= "00111100"; 
         if IN0 = '1' then nextS<=A; 
         elsif IN1 = '1' then nextS<=B; 
         else nextS<=C; 
         end if; 
    end case; 
end process; 

myFSM_synch: process(CLK,RST) 
begin 
    if (RST='1')  then currentS<=A; 
    elsif (rising_edge(CLK)) then currentS<= nextS; 
    end if; 
end process ; 

begin 

db0 : debounce 
port map 
(
    clk => CLK, 
    rst => RST, 
    input => IN0, 
    output 
end Behavioral; 

Answer 1

我通過在口岸報關重命名IN0至INP0標記了自己的代碼，宣佈在名爲INO架構的信號，在更改名字的每次出現繼續，除去外來begin並改名爲實例從成分到debounce向debouncebutton匹配組件聲明：

library ieee; 
use ieee.std_logic_1164.all; 

entity myFSM is 
    Port (CLK : in STD_LOGIC; 
      RST : in STD_LOGIC; 
      INP0 : in STD_LOGIC; -- name changed 
      IN1 : in STD_LOGIC; 
      IN2 : in STD_LOGIC; 
      LED : out STD_LOGIC_VECTOR (7 downto 0)); 
end myFSM; 

architecture Behavioral of myFSM is 
     type state is (A, B, C); 
     signal currentS, nextS: state; 

     component debouncebutton 
      Port (clk  : in std_logic;  -- connect it to the Clock of the board 
      rst  : in std_logic;  -- connect it to the Reset Button of the board   
      input : in std_logic;  -- connect it to the Push Button of the board 
      output : out std_logic  -- connect it to your circuit 
     ); 
     end component; 

     signal IN0: std_logic; --- added 
begin 
myFSM_comb: process (currentS, IN0, IN1, IN2) 
begin 
    case currentS is 
     when A => LED <= "11111111"; 
         if IN0 = '1' then nextS<=B; 
         elsif IN1 = '1' then nextS<=C; 
         else   nextS<=A; 
         end if; 
     when B => LED <= "11000011"; 
         if IN0 = '1' then nextS<=C; 
         elsif IN1 = '1' then nextS<=A; 
         else nextS<=B; 
         end if; 
     when C => LED <= "00111100"; 
         if IN0 = '1' then nextS<=A; 
         elsif IN1 = '1' then nextS<=B; 
         else nextS<=C; 
         end if; 
    end case; 
end process; 

myFSM_synch: process(CLK,RST) 
begin 
    if (RST='1')  then currentS<=A; 
    elsif (rising_edge(CLK)) then currentS<= nextS; 
    end if; 
end process ; 

-- begin -- syntax error you have a begin before process myFSB_comb 

db0 : debouncebutton --- was debounce, needs to match component declaration 
port map (
     clk => CLK, 
     rst => RST, 
     input => INP0, -- renamed input port 
     output=> IN0 -- newly declared signal INO 
    ); 

end Behavioral; 

這使新的輸入端口INP0要關聯到正規input上debouncebutton，並正式output是連接到新聲明的信號IN0。

你也可以去簡單地聲明output關聯的新信號和改變名稱IN0除myFSM的端口聲明以外的實例的所有麻煩。

您上面修改後的代碼分析。如果沒有爲debouncebutton創建實體/體系結構對，則無法對其進行詳細描述（或模擬）。