7段顯示與VHDL

Question

我目前正在與VHDL和我有7段顯示器的麻煩。我在網上發現了這個代碼，並且很難理解它到底意味着什麼。有人可以幫我理解下面的代碼是怎麼回事：

ARCHITECTURE Structure OF multi IS 
SIGNAL C : STD_LOGIC_VECTOR(2 DOWNTO 0); 
BEGIN 
LEDR <= SW; 
C(2 DOWNTO 0) <= SW(2 DOWNTO 0); 

HEX0(0) <= NOT((NOT(C(2)) AND NOT(C(1)) AND C(0)) OR 
(NOT(C(2)) AND C(1) AND C(0))); 
HEX0(1) <= NOT((NOT(C(2)) AND NOT(C(1)) AND NOT(C(0))) OR 
(NOT(C(2)) AND C(1) AND C(0))); 
HEX0(2) <= NOT((NOT(C(2)) AND NOT(C(1)) AND NOT(C(0))) OR 
(NOT(C(2)) AND C(1) AND C(0))); 
HEX0(3) <= NOT((NOT(C(2)) AND NOT(C(1)) AND C(0)) OR 
(NOT(C(2)) AND C(1) AND NOT(C(0))) OR 
(NOT(C(2)) AND C(1) AND C(0))); 
HEX0(4) <= NOT((NOT(C(2)) AND NOT(C(1)) AND NOT(C(0))) OR 
(NOT(C(2)) AND NOT(C(1)) AND C(0)) OR 
(NOT(C(2)) AND C(1) AND NOT(C(0))) OR (NOT(C(2)) AND C(1) AND C(0))); 
HEX0(5) <= NOT((NOT(C(2)) AND NOT(C(1)) AND NOT(C(0))) OR 
(NOT(C(2)) AND NOT(C(1)) AND C(0)) OR 
(NOT(C(2)) AND C(1) AND NOT(C(0))) OR (NOT(C(2)) AND C(1) AND C(0))); 
HEX0(6) <= NOT((NOT(C(2)) AND NOT(C(1)) AND NOT(C(0))) OR 
(NOT(C(2)) AND NOT(C(1)) AND C(0))); 
END Structure; 

我不明白所有NOT和OR語句中的邏輯。

非常感謝！

Answer 1

這是代碼從混淆的VHDL比賽中在線脫機時會發生的情況。

或者也許更慈善一些，初級人員於1970年代初提交了一個八進制到七段解碼器芯片（或電路板！）的原理圖，並要求用VHDL重寫它，因爲原始組件不再可用。他/她用經典的「產品總和」形式寫出來，而不是試圖將其最小化......

我相信你能做的最好的事情是把整個事情寫成查找表，位，而不用擔心邏輯的細節。

開始，每個表情...

HEX0(6) <= NOT((NOT(C(2)) AND NOT(C(1)) AND NOT(C(0))) OR 
(NOT(C(2)) AND NOT(C(1)) AND C(0))); 

，並儘量減少它

HEX0(6) <= NOT((NOT(C(2)) AND NOT(C(1))); 

並寫入每個值

C C2 C1 C0 H6 H5 H4 H3 H2 H1 H0 HEX0 
0 0 0 0 0 0 0 1 0 0 1 0001001 = 09 
1 0 0 1 0 
2 0 1 0 1 
3 0 1 1 1 
4 1 0 0 1 
5 1 0 1 1 
6 1 1 0 1 
7 1 1 1 1 

（不完整的，不能保證正確的任一...）

然後重寫這些東西：

subtype Seven_Seg is std_logic_vector(6 downto 0); 

constant Lookup : array(0 to 7) of Seven_Seg := (0 => "0001001", 
                1 => ... 
                ... 
                7 => ...); 

Hex0 <= Lookup(to_integer(unsigned(C))); 

並且完成它。