3個8位輸入比較器的Verilog

我已經改變了我原來的編碼，什麼是現在如下：3個8位輸入比較器的Verilog

module comparator (
    input wire [7:0] A, 
    input wire [7:0] B, 
    input wire [7:0] C, 
    output reg [7:0] D, 
    output reg [7:0] E, 
    output reg [7:0] F 
    ); 

    always @(*) begin 
    if (A>B && B>C) begin 
     D <= A; 
     E <= B; 
     F <= C; 
     end 
    else if (A>C && C>B) begin 
     D <= A; 
     E <= C; 
     F <= B; 
     end 
    else if (B>C && C>A) begin 
     D <= B; 
     E <= C; 
     F <= A; 
     end 
    else if (B>A && A>C) begin 
     D <= B; 
     E <= A; 
     F <= C; 
     end 
    else if (C>A && A>B) begin 
     D <= C; 
     E <= A; 
     F <= B; 
     end 
     else begin 
     D <= C; 
     E <= B; 
     F <= A; 
     end 
    end 
endmodule

這是新的測試平臺：

module testcomp; 
    reg [7:0] A, B, C; 
    wire [7:0] D, E, F; 

    comparator uut (
     .A(A), 
     .B(B), 
     .C(C), 
     .D(D), 
     .E(E), 
     .F(F) 
    ); 

    initial begin 
     A = 0; 
     repeat (3) begin 
     B = 0; 
     repeat (3) begin 
      C = 0; 
      repeat (3) begin 
      #10; 
      $display ("TESTING A=%d, B=%d, and C=%d yields D=%d, E=%d, F=%d", A, B, C, D, E, F); 
      if (A>B && B>C && D!=A && E!=B && F!=C) begin 
       $display ("ERROR!"); 
       $finish; 
      end 
      if (A>C && C>B && D!=A && E!=C && F!=B) begin 
       $display ("ERROR!"); 
       $finish; 
      end 
      if (B>A && A>C && D!=B && E!=A && F!=C) begin 
       $display ("ERROR!"); 
       $finish; 
      end 
      if (B>C && C>A && D!=B && E!=C && F!=A) begin 
       $display ("ERROR!"); 
       $finish; 
      end 
      if (C>A && A>B && D!=C && E!=A && F!=B) begin 
       $display ("ERROR!"); 
       $finish; 
      end 
      if (C>B && B>A && D!=C && E!=B && F!=A) begin 
       $display ("ERROR!"); 
       $finish; 
      end 
       C = C + 1; 
      end 
       B = B + 1; 
      end 
      A = A + 1; 
    end 
    $display ("PASSED!"); 
    $finish; 
end 
endmodule

新話題：這已經解決了我通過更改（A> B & & B> C）比較值的問題，但是當我查看結果時，仍然存在一些問題。下面是結果：

[2016-12-11 14:05:13 EST] iverilog '-Wall' design.sv testbench.sv && unbuffer vvp a.out 
TESTING A= 0, B= 0, and C= 0 yields D= 0, E= 0, F= 0 
TESTING A= 0, B= 0, and C= 1 yields D= 1, E= 0, F= 0 
TESTING A= 0, B= 0, and C= 2 yields D= 2, E= 0, F= 0 
**TESTING A= 0, B= 1, and C= 0 yields D= 0, E= 1, F= 0** 
TESTING A= 0, B= 1, and C= 1 yields D= 1, E= 1, F= 0 
TESTING A= 0, B= 1, and C= 2 yields D= 2, E= 1, F= 0 
**TESTING A= 0, B= 2, and C= 0 yields D= 0, E= 2, F= 0** 
TESTING A= 0, B= 2, and C= 1 yields D= 2, E= 1, F= 0 
TESTING A= 0, B= 2, and C= 2 yields D= 2, E= 2, F= 0 
**TESTING A= 1, B= 0, and C= 0 yields D= 0, E= 0, F= 1** 
**TESTING A= 1, B= 0, and C= 1 yields D= 1, E= 0, F= 1** 
TESTING A= 1, B= 0, and C= 2 yields D= 2, E= 1, F= 0 
**TESTING A= 1, B= 1, and C= 0 yields D= 0, E= 1, F= 1** 
TESTING A= 1, B= 1, and C= 1 yields D= 1, E= 1, F= 1 
TESTING A= 1, B= 1, and C= 2 yields D= 2, E= 1, F= 1 
TESTING A= 1, B= 2, and C= 0 yields D= 2, E= 1, F= 0 
**TESTING A= 1, B= 2, and C= 1 yields D= 1, E= 2, F= 1** 
TESTING A= 1, B= 2, and C= 2 yields D= 2, E= 2, F= 1 
**TESTING A= 2, B= 0, and C= 0 yields D= 0, E= 0, F= 2** 
TESTING A= 2, B= 0, and C= 1 yields D= 2, E= 1, F= 0 
**TESTING A= 2, B= 0, and C= 2 yields D= 2, E= 0, F= 2** 
TESTING A= 2, B= 1, and C= 0 yields D= 2, E= 1, F= 0 
**TESTING A= 2, B= 1, and C= 1 yields D= 1, E= 1, F= 2** 
**TESTING A= 2, B= 1, and C= 2 yields D= 2, E= 1, F= 2** 
**TESTING A= 2, B= 2, and C= 0 yields D= 0, E= 2, F= 2** 
**TESTING A= 2, B= 2, and C= 1 yields D= 1, E= 2, F= 2** 
TESTING A= 2, B= 2, and C= 2 yields D= 2, E= 2, F= 2 
PASSED! 
Done

你可以通過這些標記見/主演，還有它不能正確比較值的問題。這是我的代碼中的東西，還是我錯過了一個不允許它正常工作的約束？

原文：

的主要問題是，我一直陷入到設計代碼的主代碼的其他分支（我用的是（A> B> C）在代碼中比較值時）。我猜測這些數字在主代碼中根本沒有比較，問題在於我如何試圖比較這些值。你能幫我找到一種方法來正確比較三個8位輸入，以避免卡在else分支中嗎？首先十分感謝。

來源

2016-12-11 AKittensWrath

'如果（A> B I就此用下面的代碼結束> C）'不符合你的想法。試試：'如果（A> B && B> C）' – toolic

@toolic我照你說的做了，並且獲得了部分值的成功。不幸的是，仍有值不能正確比較。你可以再看看代碼，看看我在實現你的方法時是否犯了錯誤？我無法確定自己的模式，並且在測試臺上看到它高達16，這讓我頭疼，所以我嘗試了一個較小的數字。 – AKittensWrath

您還需要修復您的測試臺：'A> B> C' – toolic

我終於解決了這個問題。當價值可能相同時，我需要小心時間。

module comparator (
    input clock, 
    input wire [7:0] A, 
    input wire [7:0] B, 
    input wire [7:0] C, 
    output reg [7:0] D, 
    output reg [7:0] E, 
    output reg [7:0] F 
    ); 

    always @(*) begin 
    if (A>=B && B>=C) begin 
     D <= A; 
     E <= B; 
     F <= C; 
     end 
    else if (A>=C && C>=B) begin 
     D <= A; 
     E <= C; 
     F <= B; 
     end 
    else if (B>=C && C>=A) begin 
     D <= B; 
     E <= C; 
     F <= A; 
     end 
    else if (B>=A && A>=C) begin 
     D <= B; 
     E <= A; 
     F <= C; 
     end 
    else if (C>=A && A>=B) begin 
     D <= C; 
     E <= A; 
     F <= B; 
     end 
     else begin 
     D <= C; 
     E <= B; 
     F <= A; 
     end 
    end 
endmodule

而測試平臺：

module testcomp; 
    input clock; 
    reg [7:0] A, B, C; 
    wire [7:0] D, E, F; 

    comparator uut (
     .clock(clock), 
     .A(A), 
     .B(B), 
     .C(C), 
     .D(D), 
     .E(E), 
     .F(F) 
    ); 

    initial begin 
     A = 0; 
     repeat (255) begin 
     B = 0; 
     repeat (255) begin 
      C = 0; 
      repeat (255) begin 
      #10; 
      $display ("TESTING A=%h, B=%h, and C=%h yields D=%h, E=%h, F=%h", A, B, C, D, E, F); 
     if (A>B && B>C && D!=A && E!=B && F!=C) begin 
      $display ("ERROR!"); 
      $finish; 
     end 
     if (A>C && C>B && D!=A && E!=C && F!=B) begin 
      $display ("ERROR!"); 
      $finish; 
     end 
     if (B>A && A>C && D!=B && E!=A && F!=C) begin 
      $display ("ERROR!"); 
      $finish; 
     end 
     if (B>C && C>A && D!=B && E!=C && F!=A) begin 
      $display ("ERROR!"); 
      $finish; 
     end 
     if (C>A && A>B && D!=C && E!=A && F!=B) begin 
      $display ("ERROR!"); 
      $finish; 
     end 
     if (C>B && B>A && D!=C && E!=B && F!=A) begin 
      $display ("ERROR!"); 
      $finish; 
     end 
      C = C + 1; 
     end 
      B = B + 1; 
     end 
     A = A + 1; 
    end 
    $display ("PASSED!"); 
    $finish; 
end 
endmodule

用下面萃取（從中間拉動）的結果：

[2016-12-12 08:56:45 EST] iverilog '-Wall' design.sv testbench.sv && unbuffer vvp a.out 
TESTING A=00, B=0c, and C=05 yields D=0c, E=05, F=00 
TESTING A=00, B=0c, and C=06 yields D=0c, E=06, F=00 
TESTING A=00, B=0c, and C=07 yields D=0c, E=07, F=00 
TESTING A=00, B=0c, and C=08 yields D=0c, E=08, F=00 
TESTING A=00, B=0c, and C=09 yields D=0c, E=09, F=00 
TESTING A=00, B=0c, and C=0a yields D=0c, E=0a, F=00 
TESTING A=00, B=0c, and C=0b yields D=0c, E=0b, F=00 
TESTING A=00, B=0c, and C=0c yields D=0c, E=0c, F=00 
TESTING A=00, B=0c, and C=0d yields D=0d, E=0c, F=00 
TESTING A=00, B=0c, and C=0e yields D=0e, E=0c, F=00 
TESTING A=00, B=0d, and C=09 yields D=0d, E=09, F=00 
TESTING A=00, B=0d, and C=0a yields D=0d, E=0a, F=00 
TESTING A=00, B=0d, and C=0b yields D=0d, E=0b, F=00 
TESTING A=00, B=0d, and C=0c yields D=0d, E=0c, F=00 
TESTING A=00, B=0d, and C=0d yields D=0d, E=0d, F=00 
TESTING A=00, B=0d, and C=0e yields D=0e, E=0d, F=00 
TESTING A=00, B=0d, and C=0f yields D=0f, E=0d, F=00 
TESTING A=00, B=0d, and C=fd yields D=fd, E=0d, F=00 
TESTING A=00, B=0d, and C=fe yields D=fe, E=0d, F=00 
TESTING A=00, B=0e, and C=00 yields D=0e, E=00, F=00 
TESTING A=00, B=0e, and C=01 yields D=0e, E=01, F=00 
TESTING A=00, B=0e, and C=02 yields D=0e, E=02, F=00 
TESTING A=00, B=0e, and C=03 yields D=0e, E=03, F=00 
TESTING A=00, B=0e, and C=04 yields D=0e, E=04, F=00 
TESTING A=00, B=0e, and C=05 yields D=0e, E=05, F=00 
TESTING A=00, B=0e, and C=06 yields D=0e, E=06, F=00 
TESTING A=00, B=0e, and C=07 yields D=0e, E=07, F=00 
TESTING A=00, B=0e, and C=08 yields D=0e, E=08, F=00 
TESTING A=00, B=0e, and C=09 yields D=0e, E=09, F=00 
TESTING A=00, B=0e, and C=0a yields D=0e, E=0a, F=00 
TESTING A=00, B=0e, and C=0b yields D=0e, E=0b, F=00 
TESTING A=00, B=0e, and C=0c yields D=0e, E=0c, F=00 
TESTING A=00, B=0e, and C=0d yields D=0e, E=0d, F=00 
TESTING A=00, B=0e, and C=0e yields D=0e, E=0e, F=00 
TESTING A=00, B=0e, and C=0f yields D=0f, E=0e, F=00 
TESTING A=00, B=0e, and C=10 yields D=10, E=0e, F=00 
TESTING A=00, B=0e, and C=11 yields D=11, E=0e, F=00 
TESTING A=00, B=0f, and C=fd yields D=fd, E=0f, F=00 
TESTING A=00, B=0f, and C=fe yields D=fe, E=0f, F=00 
TESTING A=00, B=10, and C=00 yields D=10, E=00, F=00 
TESTING A=00, B=10, and C=01 yields D=10, E=01, F=00 
TESTING A=00, B=10, and C=02 yields D=10, E=02, F=00 
TESTING A=00, B=10, and C=03 yields D=10, E=03, F=00 
TESTING A=00, B=10, and C=04 yields D=10, E=04, F=00 
TESTING A=00, B=10, and C=05 yields D=10, E=05, F=00 
TESTING A=00, B=10, and C=06 yields D=10, E=06, F=00 
TESTING A=00, B=10, and C=07 yields D=10, E=07, F=00 
TESTING A=00, B=10, and C=08 yields D=10, E=08, F=00 
TESTING A=00, B=10, and C=09 yields D=10, E=09, F=00 
TESTING A=00, B=10, and C=0a yields D=10, E=0a, F=00 
TESTING A=00, B=10, and C=0b yields D=10, E=0b, F=00 
TESTING A=00, B=10, and C=0c yields D=10, E=0c, F=00 
TESTING A=00, B=10, and C=0d yields D=10, E=0d, F=00 
TESTING A=00, B=10, and C=0e yields D=10, E=0e, F=00 
TESTING A=00, B=10, and C=0f yields D=10, E=0f, F=00 
TESTING A=00, B=10, and C=10 yields D=10, E=10, F=00 
TESTING A=00, B=10, and C=11 yields D=11, E=10, F=00 
TESTING A=00, B=10, and C=12 yields D=12, E=10, F=00 
TESTING A=00, B=10, and C=13 yields D=13, E=10, F=00 
TESTING A=00, B=10, and C=fd yields D=fd, E=10, F=00 
TESTING A=00, B=10, and C=fe yields D=fe, E=10, F=00 
TESTING A=00, B=11, and C=00 yields D=11, E=00, F=00 
TESTING A=00, B=11, and C=01 yields D=11, E=01, F=00 
TESTING A=00, B=11, and C=02 yields D=11, E=02, F=00 
TESTING A=00, B=11, and C=03 yields D=11, E=03, F=00 
TESTING A=00, B=11, and C=04 yields D=11, E=04, F=00 
TESTING A=00, B=11, and C=05 yields D=11, E=05, F=00 
TESTING A=00, B=11, and C=06 yields D=11, E=06, F=00 
TESTING A=00, B=11, and C=07 yields D=11, E=07, F=00 
TESTING A=00, B=11, and C=08 yields D=11, E=08, F=00 
TESTING A=00, B=11, and C=09 yields D=11, E=09, F=00 
TESTING A=00, B=11, and C=0a yields D=11, E=0a, F=00 
TESTING A=00, B=11, and C=0b yields D=11, E=0b, F=00 
TESTING A=00, B=11, and C=0c yields D=11, E=0c, F=00 
TESTING A=00, B=11, and C=0d yields D=11, E=0d, F=00 
TESTING A=00, B=11, and C=0e yields D=11, E=0e, F=00 
TESTING A=00, B=11, and C=0f yields D=11, E=0f, F=00 
TESTING A=00, B=11, and C=10 yields D=11, E=10, F=00 
TESTING A=00, B=11, and C=11 yields D=11, E=11, F=00 
TESTING A=00, B=11, and C=12 yields D=12, E=11, F=00 
TESTING A=00, B=11, and C=13 yields D=13, E=11, F=00 
TESTING A=00, B=11, and C=14 yields D=14, E=11, F=00 
TESTING A=00, B=11, and C=15 yields D=15, E=11, F=00 
TESTING A=00, B=11, and C=16 yields D=16, E=11, F=00 
TESTING A=00, B=11, and C=17 yields D=17, E=11, F=00 
TESTING A=00, B=11, and C=fd yields D=fd, E=11, F=00 
TESTING A=00, B=11, and C=fe yields D=fe, E=11, F=00 
TESTING A=00, B=12, and C=00 yields D=12, E=00, F=00 
TESTING A=00, B=12, and C=01 yields D=12, E=01, F=00 
TESTING A=00, B=12, and C=02 yields D=12, E=02, F=00 
TESTING A=00, B=12, and C=03 yields D=12, E=03, F=00 
TESTING A=00, B=12, and C=04 yields D=12, E=04, F=00 
TESTING A=00, B=12, and C=05 yields D=12, E=05, F=00 
TESTING A=00, B=12, and C=06 yields D=12, E=06, F=00 
TESTING A=00, B=12, and C=07 yields D=12, E=07, F=00 
TESTING A=00, B=12, and C=08 yields D=12, E=08, F=00 
TESTING A=00, B=12, and C=09 yields D=12, E=09, F=00 
TESTING A=00, B=12, and C=0a yields D=12, E=0a, F=00 
TESTING A=00, B=12, and C=0b yields D=12, E=0b, F=00 
TESTING A=00, B=12, and C=0c yields D=12, E=0c, F=00 
TESTING A=00, B=12, and C=0d yields D=12, E=0d, F=00 
TESTING A=00, B=12, and C=0e yields D=12, E=0e, F=00 
TESTING A=00, B=12, and C=0f yields D=12, E=0f, F=00 
TESTING A=00, B=12, and C=10 yields D=12, E=10, F=00 
TESTING A=00, B=12, and C=11 yields D=12, E=11, F=00 
TESTING A=00, B=12, and C=12 yields D=12, E=12, F=00 
TESTING A=00, B=12, and C=13 yields D=13, E=12, F=00 
TESTING A=00, B=12, and C=14 yields D=14, E=12, F=00 
TESTING A=00, B=12, and C=15 yields D=15, E=12, F=00 
TESTING A=00, B=12, and C=16 yields D=16, E=12, F=00 
TESTING A=00, B=12, and C=17 yields D=17, E=12, F=00 
TESTING A=00, B=12, and C=fd yields D=fd, E=12, F=00 
TESTING A=00, B=12, and C=fe yields D=fe, E=12, F=00 
TESTING A=00, B=13, and C=00 yields D=13, E=00, F=00 
TESTING A=00, B=13, and C=01 yields D=13, E=01, F=00 
TESTING A=00, B=13, and C=02 yields D=13, E=02, F=00 
TESTING A=00, B=13, and C=03 yields D=13, E=03, F=00 
TESTING A=00, B=13, and C=04 yields D=13, E=04, F=00 
TESTING A=00, B=13, and C=05 yields D=13, E=05, F=00 
TESTING A=00, B=13, and C=06 yields D=13, E=06, F=00 
TESTING A=00, B=13, and C=07 yields D=13, E=07, F=00 
TESTING A=00, B=13, and C=08 yields D=13, E=08, F=00 
TESTING A=00, B=13, and C=09 yields D=13, E=09, F=00 
TESTING A=00, B=13, and C=0a yields D=13, E=0a, F=00 
TESTING A=00, B=13, and C=0b yields D=13, E=0b, F=00 
TESTING A=00, B=13, and C=0c yields D=13, E=0c, F=00 
TESTING A=00, B=13, and C=0d yields D=13, E=0d, F=00 
TESTING A=00, B=13, and C=0e yields D=13, E=0e, F=00 
TESTING A=00, B=13, and C=0f yields D=13, E=0f, F=00 
TESTING A=00, B=13, and C=10 yields D=13, E=10, F=00 
TESTING A=00, B=13, and C=11 yields D=13, E=11, F=00 
TESTING A=00, B=13, and C=12 yields D=13, E=12, F=00 
TESTING A=00, B=13, and C=13 yields D=13, E=13, F=00 
TESTING A=00, B=13, and C=14 yields D=14, E=13, F=00 
TESTING A=00, B=13, and C=15 yields D=15, E=13, F=00 
TESTING A=00, B=13, and C=16 yields D=16, E=13, F=00 
TESTING A=00, B=13, and C=17 yields D=17, E=13, F=00 
Done

來源

2016-12-12 14:09:48 AKittensWrath

3個8位輸入比較器的Verilog

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