Vhdl轉換器的案例陳述

Question

我是VHDL語言的新手，所以也許這是愚蠢的問題，但我沒有找到任何這個問題的參考。 因此，我正在研究位轉換器，它將5位的特定組合轉換爲其他組合。問題與案例陳述有關，我不知道如何將五位置於一個關聯中。

entity CONV is 
    port (ia, ib, ic, id, ie:in Bit; oa, ob, oc, od, oe:out Bit); 
end CONV; 

architecture BEH of CONV is 
signal t: bit; 
    begin 
    case ia & ib & ic & id & ie is 
    when "00010" => t <= "00011"; 
    when "00101" => t <= "00101"; 
    when "01000" => t <= "00110"; 
    when "01011" => t <= "01001"; 
    when "01110" => t <= "01010";  
    when "10001" => t <= "01100"; 
    when "10100" => t <= "10001"; 
    when "10111" => t <= "10010"; 
    when "11010" => t <= "10100"; 
    when "11101" => t <= "11000"; 
    when others => t <= "00000"; 
    end case; 
t => oa & ob & oc & od & oe; 
    end beh; 

Answer 1

entity CONV is 
    port (
     ia, ib, ic, id, ie: in Bit; 
     oa, ob, oc, od, oe: out Bit 
    ); 
end CONV; 

architecture BEH of CONV is 
    signal t: bit_vector(0 to 4); 
    subtype fivebit is bit_vector(0 to 4); 
begin 
EVALUATE: 
    process (ia, ib, ic, id, ie) 
    begin 
     case fivebit(ia & ib & ic & id & ie) is 
      when "00010" => t <= "00011"; 
      when "00101" => t <= "00101"; 
      when "01000" => t <= "00110"; 
      when "01011" => t <= "01001"; 
      when "01110" => t <= "01010";  
      when "10001" => t <= "01100"; 
      when "10100" => t <= "10001"; 
      when "10111" => t <= "10010"; 
      when "11010" => t <= "10100"; 
      when "11101" => t <= "11000"; 
      when others => t <= "00000"; 
     end case; 
    end process; 
OUTPUT: 
    (oa , ob , oc , od , oe) <= t; 
end architecture BEH; 

表達在case語句被評估必須是以下之一：與本地靜態亞型的對象的名稱（羅素的vector_in），索引名患有局部靜態索引，一個切片名稱與本地靜態範圍，返回本地靜態子類型的函數調用，或帶有本地靜態類型標記（顯示）的限定表達式或類型轉換。

想法是分析器（本地靜態意味着分析時間）可以確定表達式中元素的數量及其類型以確定案例覆蓋率。

併發信號分配的合計目標分別將聚合元素（oa，ob，oc，od，oe）與t右側的元素（Bits）相關聯。每個元素關聯只能出現一次。

case語句包含在進程（併發語句）中，因爲它是一個順序語句。爲了防止混淆，有順序和併發信號分配語句。 VHDL使用併發語句來提供並行性。

隨着測試平臺：

entity conv_test is 
end entity; 

architecture test of conv_test is 
    signal ia, ib, ic, id, ie:  bit; 
    signal oa, ob, oc, od, oe:  bit; 
    signal t:      bit_vector (0 to 4); 
    signal input:     bit_vector (0 to 4); 
begin 
DUT: 
    entity work.CONV 
     port map (
      ia => ia, ib => ib, ic => ic, id => id, ie => ie, 
      oa => oa, ob => ob, oc => oc, od => od, oe => oe 
     ) 
    ; 
TEST: 
    process 
    begin 
     wait for 10 ns; -- bit defaults to '0', others case 
     (ia, ib, ic, id, ie) <= bit_vector'("00010"); -- first case 
     wait for 10 ns; 
     (ia, ib, ic, id, ie) <= bit_vector'("00101"); 
     wait for 10 ns; 
     (ia, ib, ic, id, ie) <= bit_vector'("01000"); 
     wait for 10 ns; 
     (ia, ib, ic, id, ie) <= bit_vector'("01011"); 
     wait for 10 ns; 
     (ia, ib, ic, id, ie) <= bit_vector'("01110"); 
     wait for 10 ns; 
     (ia, ib, ic, id, ie) <= bit_vector'("10001"); 
     wait for 10 ns; 
     (ia, ib, ic, id, ie) <= bit_vector'("10100"); 
     wait for 10 ns; 
     (ia, ib, ic, id, ie) <= bit_vector'("10111"); 
     wait for 10 ns; 
     (ia, ib, ic, id, ie) <= bit_vector'("11010"); 
     wait for 10 ns; 
     (ia, ib, ic, id, ie) <= bit_vector'("11101"); 
     wait for 10 ns; 
     (ia, ib, ic, id, ie) <= bit_vector'("11111"); -- others case 
     wait for 10 ns; 
     wait;        -- one time only 
    end process; 
SIM_INPUT: 
    input <= (ia & ib & ic & id & ie); -- for ease of viewing in waveform display 
RESULT: 
    t <= (oa & ob & oc & od & oe); 
end architecture; 

您可以測試CONV：

注意，測試過程可以重新編寫簡單得多分配給輸入，而不是總（ ia，ib，ic，id，ie），通過使用

(ia , ib , ic , id , ie) <= input; 

在SIM_INPUT聲明：

TEST: 
    process 
    begin 
     wait for 10 ns; -- bit defaults to '0', others case 
     input <= "00010"; -- first case 
     wait for 10 ns; 
     input <= "00101"; 
     wait for 10 ns; 
     input <= "01000"; 
     wait for 10 ns; 
     input <= "01011"; 
     wait for 10 ns; 
     input <= "01110"; 
     wait for 10 ns; 
     input <= "10001"; 
     wait for 10 ns; 
     input <= "10100"; 
     wait for 10 ns; 
     input <= "10111"; 
     wait for 10 ns; 
     input <= "11010"; 
     wait for 10 ns; 
     input <= "11101"; 
     wait for 10 ns; 
     input <= "11111"; -- others case 
     wait for 10 ns; 
     wait;        -- one time only 
    end process; 
SIM_INPUT: 
    (ia, ib, ic, id, ie) <= input; -- for ease of viewing in waveform display 

並獲得相同的波形顯示

Answer 2

試試這個：

architecture BEH of CONV is 
signal vector_in : bit_vector(4 downto 0); 
signal vector_out : bit_vector(4 downto 0); 
begin 
case vector_in is 
    when "00010" => vector_out <= "00011"; 
    when "00101" => vector_out <= "00101"; 
    when "01000" => vector_out <= "00110"; 
    when "01011" => vector_out <= "01001"; 
    when "01110" => vector_out <= "01010";  
    when "10001" => vector_out <= "01100"; 
    when "10100" => vector_out <= "10001"; 
    when "10111" => vector_out <= "10010"; 
    when "11010" => vector_out <= "10100"; 
    when "11101" => vector_out <= "11000"; 
    when others => vector_out <= "00000"; 
end case; 

vector_in <= (ia & ib & ic & id & ie); 

oa <= vector_out(4); 
ob <= vector_out(3); 
oc <= vector_out(2); 
od <= vector_out(1); 
oe <= vector_out(0); 

有意義嗎？

Answer 3

你可以把所有的投入有點像載體說@Russell。然後位向量中的每個位代表一個輸入。這使事情變得更容易。

而且情況下語句是順序語句（即，它們必須被放入一個過程或過程或功能）。

entity CONV is 
    port (inp : in Bit_Vector(4 downto 0); -- [ai, bi, ci, di, ei] 
     outp: out Bit_Vector(4 downto 0)); -- [ao, bo, co, do, eo] 
end CONV; 

architecture BEH of CONV is 
begin 
    process (inp) 
    begin   
    case inp is 
     when "00010" => outp <= "00011"; 
     when "00101" => outp <= "00101"; 
     when "01000" => outp <= "00110"; 
     when "01011" => outp <= "01001"; 
     when "01110" => outp <= "01010";  
     when "10001" => outp <= "01100"; 
     when "10100" => outp <= "10001"; 
     when "10111" => outp <= "10010"; 
     when "11010" => outp <= "10100"; 
     when "11101" => outp <= "11000"; 
     when others => outp <= "00000"; 
    end case; 
    end process; 
end beh; 

如果你真的想使用單比特可讀性 - 或其他原因，正好連接和中斷他們過程之外。
對於引腳規劃，您只需要連接ai至inp[4],bi至inp[3]等。