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嗨，我正在使用下面的代碼來設計一個n位計數器。 根據開始和結束，我想實例化向上或向下計數器。Verilog中的格式錯誤
但我得到了「格式錯誤的陳述」。請幫忙。
module nbitUpCounter(startc,endc , clk, rst_n,actlow,count);
parameter n = 7;
output reg [n:0] count;
input [n:0] startc;
input [n:0] endc;
input clk;
input rst_n;
input actlow;
// Increment count on clock
always @(actlow or posedge clk or negedge rst_n)
begin
if (actlow == 0)
begin
if (rst_n==0)
count = startc;
else if (count==endc) count=startc;
else count = count + 1;
end
end
endmodule
module nbitDownCounter(startc,endc , clk, rst_n,actlow,count);
parameter n = 7;
output reg [n:0] count;
input [n:0] startc;
input [n:0] endc;
input clk;
input rst_n;
input actlow;
// Increment count on clock
always @(actlow or posedge clk or negedge rst_n)
begin
if (actlow == 0)
begin
if (rst_n==0)
count = startc;
else if (count==endc) count=startc;
else count = count - 1;
end
end
endmodule
module Init(startc,endc , clk, rst_n,actlow,count);
parameter n = 7;
output wire [n:0] count;
input [n:0] startc;
input [n:0] endc;
input clk;
input rst_n;
input actlow;
generate
initial
begin
if(startc>endc)
nbitDownCounter c(startc, endc, C_t,rst_t,actlow,count);
end
endgenerate
endmodule
module Testbench;
reg [7:0] startc, endc;
reg C_t, rst_t;
reg actlow;
wire [7:0] outc;
initial
begin
//case 0
startc <= 8'b00000011; endc <= 8'b0000001;
//Init i(startc,endc,C_t,rst_t,actlow,count);
actlow<=0;
C_t <=1; rst_t <=0;
#1 $display("count = %b",outc);
//case1
rst_t<=1;C_t<=0;C_t<=1;
#1 $display("count = %b",outc);
//Case3
C_t<=0;C_t<=1;
#1 $display("count = %b",outc);
//Case3
C_t<=0;C_t<=1;
#1 $display("count = %b",outc);
end
endmodule
請發佈您的錯誤信息的全部，希望它告訴你更多。 – Tim