在我的VHDL代碼錯誤，但我似乎無法弄清楚爲什麼

Question

我寫了一個VHDL代碼顯示的狀態圖（augh，無法發佈圖像，因爲我是一個新用戶）。但是，當我編譯它時，它說有錯誤：第16行中有 ：進程（clk） - 在解析時檢測到語法錯誤 第21行：else - 在解析時檢測到語法錯誤 第23行： 萬一; - 解析時檢測到語法錯誤。

這是我的代碼：

library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_arith.all; 
use IEEE.std_logic_unsigned.ALL; 
entity memory_controller is 
port(clk: in std_logic; 
reset: in std_logic; 
bus_id: in std_logic_vector(7 downto 0); 
read_write, burst: in std_logic; 
oe, we, addr_1, addr_2: out std_logic 
); 
end memory_controller; 
architecture behavioral of memory_controller is 
type statetype is (idle, decision, wr, rd1, rd2, rd3, rd4); 
signal present_state, next_state : statetype; 
process(clk) [LINE 16] 
begin 
if (rising_edge(clk)) then 
    if (reset ='0') then 
     present_state <= next_state; 
    else [LINE 21] 
     present_state <= idle; 
    end if; [LINE 23] 
end if; 
end process; 
process(present_state, read_write, ready, burst) 
begin 
case present_state is 
when idle => 
    oe => '0'; we=> '0'; addr_1=> '0'; addr_2=> '0'; 
if(bus_id = "11110011") then 
    next_state <= decision; 
else 
    next_state <= idle; 
end if; 
when decision => 
    if (read_write = '1') 
     then next_state <= rd1; 
    else next_state <= wr; 
end if; 
when wr => 
we = '1'; 
    if (ready = '1') 
then next_state <= idle; 
else 
next_state <= wr; 
end if; 
when rd1 => 
oe = '1'; 
addr_1 = addr_1 + '1'; 
addr_2 = addr_2 + '1'; 
if(ready = '0') then 
next_state <= rd1; 
if(burst = '0') then 
next_state <= idle; 
else next_state <= rd2; 
end if; 
when rd2 => 
oe = '1'; 
addr_1 = addr_1 + '1'; 
addr_2 = addr_2 + '1'; 
if(ready = '1') then 
next_state => rd3; 
else 
next_state => rd2; 
end if; 
when rd3 => 
oe = '1'; 
addr_1 = addr_1 + '1'; 
addr_2 = addr_2 + '1'; 
if(ready = '1') then 
next_state => rd4; 
else 
next_state => rd3; 
when rd4 => 
oe = '1'; 
addr_1 = addr_1 + '1'; 
addr_2 = addr_2 + '1'; 
if(ready = '1') 
then next_state => idle; 
else next_state => rd4; 
end if; 
end case; 
end process; 
end behavioral; 

的語法是完全正確的，我不明白爲什麼這是一個錯誤。什麼可能是錯的？

此外，我想使用assert語句的情況準備= 0，突發= 0和準備= 0和突發= 1，但我不知道如何實現它們在主代碼中。

我已經強調線16，21和23

任何幫助將是巨大的。

Answer 1

一個VHDL模塊的形式通常是：

entity MODULENAME is 
    <Port description> 
end MODULENAME; 

architecture behavioral of MODULENAME is 
    <signal declarations and similar> 
begin 
    <synchronous and combinatorial logic statements> 
end architecture behavioral; 

你所缺乏的是你的信號聲明後begin。也就是說，改變

architecture behavioral of memory_controller is 
    type statetype is (idle, decision, wr, rd1, rd2, rd3, rd4); 
    signal present_state, next_state : statetype; 

    process(clk) [LINE 16] 
    begin 
    if (rising_edge(clk)) then 

要：

architecture behavioral of memory_controller is 
    type statetype is (idle, decision, wr, rd1, rd2, rd3, rd4); 
    signal present_state, next_state : statetype; 

begin 

    process(clk) [LINE 16] 
    begin 
    if (rising_edge(clk)) then 

Answer 2

由於Sonicwave所指出的，你缺少你的第一個語句之前begin關鍵字。

還有幾個語法錯誤。 信號分配使用向左的箭頭：

• 沒有oe => '0';但oe <= '0';
• 沒有we = '1';但we <= '1';

如果您使用的編譯器直接反饋的編輯器，你可以節省自己很多的時間。