SystemVerilog接口多路複用器

Question

我對systemverilog很陌生，試圖構建一個systemverilog測試平臺。 我有一個應通過多路複用器連接到兩個外部模塊之一的DUT。我想在模擬期間切換連接，我想使用systemverilog接口來連接DUT和多路複用器之間的連接，以及多路複用器和兩個外部模塊之間的連接。接口中的信號是雙向的。

我在編寫多路複用器時遇到了麻煩。對於當前的實現，我得到一個錯誤，表達的LHS不能成爲電線。如果我將界面中的類型更改爲邏輯，則會出現雙向信號無法實現的錯誤。 我試圖谷歌，但我沒有找到任何教程連接接口的界面。這不可能嗎？還是有更好的方式來做我想做的事情？

到目前爲止，我有以下幾點：

interface flash_connect_interface; 
    wire interface_f_cle; 
    wire interface_f_ale; 
endinterface: flash_connect_interface 


module flash_connect_testbench_top;  
[...] 
    // Interfaces 
    flash_connect_interface flash_connect_interface_i0(); 
    flash_connect_interface flash_connect_interface_i1(); 
    flash_connect_interface flash_connect_interface_i2(); 

    // Connecting DUT to interface 
    flash_connect flash_connect_i0( 
    .flash_connect_interface_i(flash_connect_interface_i0), 
); 

    // Multiplexer 
    flash_connect_mux mux1(
    .flash_connect_interface_i_0(flash_connect_interface_i0), 
    .flash_connect_interface_i_1(flash_connect_interface_i1), 
    .flash_connect_interface_i_2(flash_connect_interface_i2), 
    .select(sel) 
); 

    nand_model nand_model0 (
     .Cle  (flash_connect_interface_i1.interface_f_cle), 
     .Ale  (flash_connect_interface_i1.interface_f_ale), 
     ); 

    nand_model nand_model1 (
     .Cle  (flash_connect_interface_i2.interface_f_cle), 
     .Ale  (flash_connect_interface_i2.interface_f_ale), 
     ); 
[...] 
endmodule // end testbench_top 



module flash_connect_mux(
    flash_connect_interface flash_connect_interface_i_0, 
    flash_connect_interface flash_connect_interface_i_1, 
    flash_connect_interface flash_connect_interface_i_2, 
    input select 
); 

    always_comb begin 
    // *** Here is the problem *** 
    if (select == 1'b0) flash_connect_interface_i_1 = flash_connect_interface_i_0;  
    else flash_connect_interface_i_2 = flash_connect_interface_i_0; 
    end 

endmodule 

Answer 1

在這種情況下，接口只是捆綁電線。你的代碼似乎沒有任何明顯的錯誤。但是，如果您試圖根據選擇信號將接口直接分配給對方，則無法工作。您將需要根據選擇信號分別分配所有電線。沒有什麼特別的複用接口。

下面的代碼會混合使用。

interface flash_connect_interface; 
    wire interface_f_cle; 
    wire interface_f_ale; 
endinterface: flash_connect_interface 

module nand_model (inout Cle , inout Ale) ; // Sample nand model 

reg r = 1; 
assign Cle = r?1:1'bz; 
assign Ale = r?1:1'bz; 

endmodule 

module flash_connect_mux (flash_connect_interface flash_connect_interface_i_0 , flash_connect_interface flash_connect_interface_i_1 , flash_connect_interface 

flash_connect_interface_i_2 ,input [3:0] select) ; 
    // Interconnect interface assignment 
    assign flash_connect_interface_i_0.interface_f_cle = (select== 0) ? flash_connect_interface_i_1.interface_f_cle : flash_connect_interface_i_2.interface_f_cle; 
    assign flash_connect_interface_i_0.interface_f_ale = (select== 0) ? flash_connect_interface_i_1.interface_f_ale : flash_connect_interface_i_2.interface_f_ale; 
endmodule 

    module flash_connect (flash_connect_interface flash_connect_interface_i) ; 

     //check flash_connect_interface_i.interface_f_cle ; 
     //check flash_connect_interface_i.interface_f_ale ; 
    endmodule 

module flash_connect_testbench_top; 

reg [3:0] select ; 
    // Interfaces 
    flash_connect_interface flash_connect_interface_i0(); 
    flash_connect_interface flash_connect_interface_i1(); 
    flash_connect_interface flash_connect_interface_i2(); 

    // Connecting DUT to interface 
    flash_connect flash_connect_i0(
    .flash_connect_interface_i(flash_connect_interface_i0) 
); 

    // Multiplexer 
    flash_connect_mux mux1(
    .flash_connect_interface_i_0(flash_connect_interface_i0), 
    .flash_connect_interface_i_1(flash_connect_interface_i1), 
    .flash_connect_interface_i_2(flash_connect_interface_i2), 
    .select(select) 
); 

    nand_model nand_model0 (
     .Cle  (flash_connect_interface_i1.interface_f_cle), 
     .Ale  (flash_connect_interface_i1.interface_f_ale) 
     ); 

    nand_model nand_model1 (
     .Cle  (flash_connect_interface_i2.interface_f_cle), 
     .Ale  (flash_connect_interface_i2.interface_f_ale) 
     ); 

endmodule // end testbench_top 

鏈接接口教程 - https://www.doulos.com/knowhow/sysverilog/tutorial/interfaces/