Xilinx FFT v8.0內核示例testbench

Question

我想在Virtex 7上使用賽靈思FFTv8.0內核計算一系列16位輸入值的DFT變換，但我對理解數據表有些麻煩。

更具體地說，我使用了一個標準的自動生成的測試平臺（見下文），但輸出始終爲零。即使通過數據表和「Jim Wu的FPGA博客」（http://myfpgablog.blogspot.de/2010/07/fft-results-from-matlab-fft-bit.html）很多次，我仍然不知道如何使用它。我覺得我是在覈心的多個輸入/輸出迷茫..

`timescale 1ns/1ps 

//////////////////////////////////////////////////////////////////////////////// 
// Company: 
// Engineer: 
// 
// Create Date: 14:25:20 05/14/2015 
// Design Name: fft_core 
// Module Name: C:/Users/Alberto/Documents/MEGA/Master II/Master Thesis/test_fft/fft_tb.v 
// Project Name: test_fft 
// Target Device: 
// Tool versions: 
// Description: 
// 
// Verilog Test Fixture created by ISE for module: fft_core 
// 
// Dependencies: 
// 
// Revision: 
// Revision 0.01 - File Created 
// Additional Comments: 
// 
//////////////////////////////////////////////////////////////////////////////// 

module fft_tb; 

    // Inputs 
    reg aclk; 
    reg s_axis_config_tvalid; 
    reg s_axis_data_tvalid; 
    reg s_axis_data_tlast; 
    reg m_axis_data_tready; 
    reg [7:0] s_axis_config_tdata; 
    reg [31:0] s_axis_data_tdata; 

    // Outputs 
    wire s_axis_config_tready; 
    wire s_axis_data_tready; 
    wire m_axis_data_tvalid; 
    wire m_axis_data_tlast; 
    wire event_frame_started; 
    wire event_tlast_unexpected; 
    wire event_tlast_missing; 
    wire event_status_channel_halt; 
    wire event_data_in_channel_halt; 
    wire event_data_out_channel_halt; 
    wire [31:0] m_axis_data_tdata; 

    // generate clk 
    always #5 aclk =! aclk; 

    // Instantiate the Unit Under Test (UUT) 
    fft_core uut (
     .aclk(aclk), 
     .s_axis_config_tvalid(s_axis_config_tvalid), 
     .s_axis_data_tvalid(s_axis_data_tvalid), 
     .s_axis_data_tlast(s_axis_data_tlast), 
     .m_axis_data_tready(m_axis_data_tready), 
     .s_axis_config_tready(s_axis_config_tready), 
     .s_axis_data_tready(s_axis_data_tready), 
     .m_axis_data_tvalid(m_axis_data_tvalid), 
     .m_axis_data_tlast(m_axis_data_tlast), 
     .event_frame_started(event_frame_started), 
     .event_tlast_unexpected(event_tlast_unexpected), 
     .event_tlast_missing(event_tlast_missing), 
     .event_status_channel_halt(event_status_channel_halt), 
     .event_data_in_channel_halt(event_data_in_channel_halt), 
     .event_data_out_channel_halt(event_data_out_channel_halt), 
     .s_axis_config_tdata(s_axis_config_tdata), 
     .s_axis_data_tdata(s_axis_data_tdata), 
     .m_axis_data_tdata(m_axis_data_tdata) 
    ); 

    initial begin 
     // Initialize Inputs 
     aclk = 0; 
     s_axis_config_tvalid = 0; 
     s_axis_data_tvalid = 0; 
     s_axis_data_tlast = 0; 
     m_axis_data_tready = 0; 
     s_axis_config_tdata = 0; 
     s_axis_data_tdata = 0; 

     // Wait 100 ns for global reset to finish 
     #150; 

     s_axis_config_tvalid = 1; 
     s_axis_data_tvalid = 1; 
     //s_axis_data_tlast = 1; 
     m_axis_data_tready = 1; 
     s_axis_config_tdata = 1; 
     s_axis_data_tdata = 1; 

     // Add stimulus here 

     // Some random inputs (just to understand how it works): 
     s_axis_config_tdata = 8'b00000001; // FFT desired (and not IFFT) 
     s_axis_data_tdata = 32'h00005678; // I have a real input signal, so the upper half (corresponding to the immaginary part) is zero 
     #10; 
     s_axis_config_tdata = 8'b00000001; 
     s_axis_data_tdata = 32'h00001121; 
     #10; 
     s_axis_config_tdata = 8'b00000001; 
     s_axis_data_tdata = 32'h00001516; 
     #10; 
     s_axis_config_tdata = 8'b00000001; 
     s_axis_data_tdata = 32'h00001920; 
     #10; 
     s_axis_config_tdata = 8'b00000001; 
     s_axis_data_tdata = 32'h00001121; 
     #10; 
     s_axis_config_tdata = 8'b00000001; 
     s_axis_data_tdata = 32'h00001516; 
     #10; 
     s_axis_config_tdata = 8'b00000001; 
     s_axis_data_tdata = 32'h00001920; 
     #10; 
     s_axis_config_tdata = 8'b00000001; 
     s_axis_data_tdata = 32'h00001121; 
     #10; 
     s_axis_config_tdata = 8'b00000001; 
     s_axis_data_tdata = 32'h00001516; 
     #10; 
     s_axis_config_tdata = 8'b00000001; 
     s_axis_data_tdata = 32'h00001920; 
     #10; 
     s_axis_config_tdata = 8'b00000001; 
     s_axis_data_tdata = 32'h00001121; 
     #10; 
     s_axis_config_tdata = 8'b00000001; 
     s_axis_data_tdata = 32'h00001516; 
     #10; 
     s_axis_config_tdata = 8'b00000001; 
     s_axis_data_tdata = 32'h00001920; 
     #10; 
     s_axis_config_tdata = 8'b00000001; 
     s_axis_data_tdata = 32'h00001121; 
     #10; 
     s_axis_config_tdata = 8'b00000001; 
     s_axis_data_tdata = 32'h00001516; 
     #10; 
     s_axis_config_tdata = 8'b00000001; 
     s_axis_data_tdata = 32'h00001920; 
     #10; 


    end 

endmodule 

這裏是波形和我使用的核心配置的一些截圖（我還沒有的權力，直接張貼）： https://www.dropbox.com/s/0ejccc4dm6zdw7h/FFT.zip?dl=0

有沒有人有解釋或工作測試平臺（可能寫在Verilog中）處理數據與此ip核心？

謝謝你提前

Answer 1

最後我有點解決了我的問題。核心在交付數據之前有巨大的延遲（幾個我們）。 所以如果別人有同樣的問題，不要猶豫，大大增加模擬時間，它可能會解決您的問題。