未申報端口的Verilog錯誤

Question

我試圖做固定點師在Verilog和我遇到與不宣口兩個錯誤（R2和C2）。我不知道爲什麼會發生這種情況，因爲在C和Q它的作品。你能幫我嗎？謝謝。

module tema1(a,b,q,c,r); 

    input[7:0] a; 
    input[7:0] b; 

    output[15:0] q; 
    reg[15:0] q; 
    output[7:0] r2; 
    output[7:0] c; 
    output[7:0] c2; 
    output[7:0] r; 
reg[7:0] r2; 
    reg[7:0] c; 
    reg[7:0] c2; 
    reg[7:0] r; 

    always @(*) 
     begin 


     c = 8'b00000000; 
     r = a; 
     c2 = 8'b00000000; 

     repeat (30) 
        begin 
         if (r >= b) 
          begin 
         c = c + 1; 
         r = r - b; 
          end 
        end 

     $display("c=%d", c); 
     $display("r=%d",r); 



       r = r * 10; 
       r2 = r; 
       repeat (30) 
        begin 
         if (r2 >= b ) 
          begin 
          c2 = c2 + 1; 
         r2= r2 - b; 
          end 
        q[8:7]=c2; 

        end 


       r = r * 10; 
       r2 = r; 
       repeat (30) 
        begin 
         if (r2 >= b ) 
          begin 
          c2 = c2 + 1; 
         r2= r2 - b; 
          end 
         q[7:6]=c2; 

        end 


       r = r * 10; 
       r2 = r; 
       repeat (30) 
        begin 
         if (r2 >= b ) 
          begin 
          c2 = c2 + 1; 
         r2= r2 - b; 
          end 
         q[6:5]=c2; 

        end 


       r = r * 10; 
       r2 = r; 
       repeat (30) 
        begin 
         if (r2 >= b ) 
          begin 
          c2 = c2 + 1; 
         r2= r2 - b; 
          end 
         q[5:4]=c2; 

        end 


       r = r * 10; 
       r2 = r; 
       repeat (30) 
        begin 
         if (r2 >= b ) 
          begin 
          c2 = c2 + 1; 
         r2= r2 - b; 
          end 
         q[4:3]=c2; 

        end 

       r = r * 10; 
       r2 = r; 
       repeat (30) 
        begin 
         if (r2 >= b ) 
          begin 
          c2 = c2 + 1; 
         r2= r2 - b; 
          end 
         q[3:2]=c2; 

        end 


       r = r * 10; 
       r2 = r; 
       repeat (30) 
        begin 
         if (r2 >= b ) 
          begin 
          c2 = c2 + 1; 
         r2= r2 - b; 
          end 
         q[2:1]=c2; 

        end 


       r = r * 10; 
       r2 = r; 
       repeat (30) 
        begin 
         if (r2 >= b ) 
          begin 
          c2 = c2 + 1; 
         r2= r2 - b; 
          end 
        q[1:0]=c2; 

        end 






end 

endmodule 

Answer 1

，因爲你宣佈r2和c2爲輸出您收到此錯誤，但它們不會出現在端口列表中。您使用的語法來自Verilog-1995，您可能必須定義端口最多3次（端口列表，方向和數據類型中的1個位置）。請使用來自的Verilog-2001的更新語法（現在的SystemVerilog）

module tema1(
     input[7:0] a,b, 
     output reg [15:0] q, 
     output reg [7:0] c, r 
     ); 
// internal 
     reg[7:0] c2, r2;