將verilog測試臺輸出保存到文件

Question

我已經寫了一個小的Verilog代碼和它的測試平臺。它包含在下面.. 我想將測試臺結果捕獲到一個文件（AA2.txt）。但是，當我運行模擬器時，「結果」顯示在監視器上，AA2.txt文件爲空。 你能幫我弄清楚我錯過了什麼嗎？你能解釋一下嗎？謝謝。 Bhal Tulpule

`timescale 1ns/1ps 

//////////////////////////////////////////////////////////////////////////////// 
// Company: 
// Engineer: 
// 
// Create Date: 16:57:34 12/04/2014 
// Design Name: ADC_SAMPLE 
// Module Name: C:/Xilinx131/SOC/SOC501V2/ADC_SAMPLE_tb.v 
// Project Name: SOC501V2 
// Target Device: 
// Tool versions: 
// Description: 
// 
// Verilog Test Fixture created by ISE for module: ADC_SAMPLE for review with Honeywell 
// 
// Dependencies: 
// 
// Revision: 
// Revision 0.01 - File Created 
// Additional Comments: 
// 
//////////////////////////////////////////////////////////////////////////////// 

module ADC_SAMPLE_tb; 

    // Inputs 
    reg CLK; 
    reg ASM_SEL; 
    reg [11:0] ADC_BUS; 
    reg [7:0] ADC_Wait_Time; 

    // Outputs 
    wire [7:0] ASM_HB; 
    wire [7:0] ASM_LB; 
    wire AS_SConv; 
    wire AS_OE; 
    wire ASM_FLAG; 
    wire [3:0] S; 

    parameter PERIOD = 100; 
    parameter real DUTY_CYCLE = 0.5; 
    parameter OFFSET = 0; 


    // Instantiate the Unit Under Test (UUT) 
    ADC_SAMPLE uut (
     .CLK(CLK), 
     .ASM_SEL(ASM_SEL), 
     .ADC_BUS(ADC_BUS), 
     .ADC_Wait_Time(ADC_Wait_Time), 
     .ASM_HB(ASM_HB), 
     .ASM_LB(ASM_LB), 
     .AS_SConv(AS_SConv), 
     .AS_OE(AS_OE), 
     .ASM_FLAG(ASM_FLAG), 
     .S(S) 
    ); 

    initial begin 
     // Initialize Inputs 
     CLK = 0; 
     ASM_SEL = 1; 
     ADC_BUS = 12'hABC; 
     ADC_Wait_Time = 4; 
    end 

    initial  
    begin 
     #OFFSET; 
     forever 
     begin 
      CLK = 1'b1; 
      #(PERIOD-(PERIOD*DUTY_CYCLE)) CLK = 1'b0; 
      #(PERIOD*DUTY_CYCLE); 
     end 
    end 


    initial begin 
     // Wait 100 ns for global reset to finish 
     // Add stimulus here 
     #200 ASM_SEL=1; 
     #150 ASM_SEL=0; 

    end 


    integer h1; 

    initial 
    h1 = $fopen("AA2.dmp");//did not work as a seperate init/begin block.. 


    begin//No initial for $stobe 
    always @ (posedge CLK) 
    $monitor(h1," %d, %b, %b, %h, %h, %b, %b, %b, %h", 
       h1,CLK, ASM_SEL,/* ADC_BUS,ADC_Wait_Time,*/ASM_HB,ASM_LB, 
       AS_SConv, AS_OE, ASM_FLAG, 
       S); end 

    initial 
    begin 
    $display("ADC_SAMPLE_tb simulator output"); 
    $display ("h1,CLK, ASM_SEL,ASM_HB,ASM_LB,AS_SConv, AS_OE, ASM_FLAG,S"); 

    end 
    initial 
// begin 
    #2000 $fclose (h1); 
// end 


endmodule 

Answer 1

我想你可能只需要使用

• $fwrite而不是$display
• $fmonitor而不是$monitor

的$display和$monitor命令只寫到標準輸出，但是$fwrite和$fmonitor將允許您將輸出寫入您打開的文件h1。

Answer 2

更新的測試臺附加。現在得到警告「文件/多通道描述符（2）傳遞給無效的$ fclose」。 AA2.txt文件是emply。使用$ fwrite（而不是$ fmonitor），它可以工作，但有相同的警告。我應該忽略這個警告嗎？ 我也嘗試使用「重置」（SEE CODE）開始/停止寫入文件，但重置始終爲1，因此沒有輸出。你可以解釋嗎 ？ REPOSITN GMODIFIED CODE ..

``timescale 1ns/1ps 

//////////////////////////////////////////////////////////////////////////////// 
// Company: 
// Engineer: 
// 
// Create Date: 16:57:34 12/04/2014 
// Design Name: ADC_SAMPLE 
// Module Name: C:/Xilinx131/SOC/SOC501V2/ADC_SAMPLE_tb.v 
// Project Name: SOC501V2 
// Target Device: 
// Tool versions: 
// Description: 
// 
// Verilog Test Fixture created by ISE for module: ADC_SAMPLE for review with Honeywell 
// 
// Dependencies: 
// 
// Revision: 
// Revision 0.01 - File Created 
// Additional Comments: 
// 
//////////////////////////////////////////////////////////////////////////////// 

module ADC_SAMPLE_tb; 

    // Inputs 
    reg CLK; 
    reg ASM_SEL; 
    reg [11:0] ADC_BUS; 
    reg [7:0] ADC_Wait_Time; 

    // Outputs 
    wire [7:0] ASM_HB; 
    wire [7:0] ASM_LB; 
    wire AS_SConv; 
    wire AS_OE; 
    wire ASM_FLAG; 
    wire [3:0] S; 

    parameter PERIOD = 100; 
    parameter real DUTY_CYCLE = 0.5; 
    parameter OFFSET = 0; 


    // Instantiate the Unit Under Test (UUT) 
    ADC_SAMPLE uut (
     .CLK(CLK), 
     .ASM_SEL(ASM_SEL), 
     .ADC_BUS(ADC_BUS), 
     .ADC_Wait_Time(ADC_Wait_Time), 
     .ASM_HB(ASM_HB), 
     .ASM_LB(ASM_LB), 
     .AS_SConv(AS_SConv), 
     .AS_OE(AS_OE), 
     .ASM_FLAG(ASM_FLAG), 
     .S(S) 
    ); 

    initial begin 
     // Initialize Inputs 
     CLK = 0; 
     ASM_SEL = 1; 
     ADC_BUS = 12'hABC; 
     ADC_Wait_Time = 4; 
    end 

    initial  
    begin 
     #OFFSET; 
     forever 
     begin 
      CLK = 1'b1; 
      #(PERIOD-(PERIOD*DUTY_CYCLE)) CLK = 1'b0; 
      #(PERIOD*DUTY_CYCLE); 
     end 
    end 


    initial begin 
     // Wait 100 ns for global reset to finish 
     // Add stimulus here 
     #200 ASM_SEL=1; 
     #150 ASM_SEL=0; 

    end 


    integer h1; 
    reg reset; 

    initial begin 
    reset = 0; 
    @(negedge ASM_FLAG) reset = 1;//at completion of sim, ASM_FLAG goes 0; 
    end 

    initial begin 
    $display("ADC_SAMPLE_tb simulator output"); 
    $display ("h1,CLK, ASM_SEL,ASM_HB,ASM_LB,AS_SConv, AS_OE, ASM_FLAG,S"); 
    end 

    initial begin 
    h1 = $fopen("AA2.txt");//did not work as a seperate init/begin block.. 
    end 



    always @ (posedge CLK) 
    begin 
    repeat (10) 
// while (reset == 0) 
    begin 
    $fwrite(h1,"%d,%b,%b,%b,%h,%h,%b,%b,%b,%h,\n", 
       h1,reset,CLK, ASM_SEL,/* ADC_BUS,ADC_Wait_Time,*/ASM_HB,ASM_LB, 
       AS_SConv, AS_OE, ASM_FLAG, 
       S); 
    end 
    $fclose (h1); 

    end 
endmodule 

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