2017-08-11 114 views
1

我在用的代碼從本網站code看到模擬輸出賽靈思而不是數字輸出

entity triangular is 
port (clk : in std_logic; 
    wave_out : out std_logic_vector(7 downto 0); 
    reset :in std_logic 
); 
end triangular; 

architecture Behavioral of triangular is 

signal count,count2 : integer := 0; 
signal direction : std_logic := '0'; 

begin 

process(clk,reset) 
begin 
if(reset = '1') then 
count <= 0; 
count2 <= 129; 
elsif(rising_edge(clk)) then 
--"direction" signal determines the direction of counting - up or down 
if(count = 253) then 
    count <= 0; 
    if(direction = '0') then 
     direction <= '1'; 
     count2 <= 126; 
    else 
     direction <= '0'; 
     count2 <= 129; 
    end if; 
else 
    count <= count + 1; 
end if; 
if(direction = '0') then 
    if(count2 = 255) then 
     count2 <= 0; 
    else 
     count2 <= count2 + 1; --up counts from 129 to 255 and then 0 to 127 
    end if; 
else 
    if(count2 = 255) then 
     count2 <= 0; 
    else 
     count2 <= count2 - 1; --down counts from 126 to 0 and then 255 to 128 
    end if; 
end if; 

end if; 
end process; 

wave_out <= conv_std_logic_vector(count2,8); 

end Behavioral; 

,我以數字形式獲得輸出,但我想作爲網站鏈接給獲取輸出。我怎樣才能做到這一點?我是VHDL新手,將其作爲工作分配。

output image
(點擊放大)

+0

您只需要縮小波形並展開'wave_out'總線。 – Qiu

+2

我假設您正在使用Vivado。在波形窗口中選擇'wave_out'總線。右鍵點擊並轉到「波形樣式」選項。你可以在那裏選擇Analog。 –

回答

0

在賽靈思ISE仿真模擬結果只在數字值,而不是ISIM可以使用ModelSim仿真 在這種ModelSim仿真模擬數據選項可用 在Vivado模擬器也有模擬數據查看選項