簡單的添加不工作，timming問題

Question

首先出現的是這個簡單的加法器的實體：

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use ieee.std_logic_unsigned.all; 
use ieee.std_logic_misc.all; 
use ieee.numeric_std.all; 

entity adder is 
    Port (a : in STD_LOGIC_VECTOR(31 downto 0); 
      b : in STD_LOGIC_VECTOR(31 downto 0); 
      alu_out : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0') 
      ); 
end adder; 

architecture Behavioral of adder is 
    signal result_ext:STD_LOGIC_VECTOR(32 downto 0) := (others => '0'); 
    signal result:STD_LOGIC_VECTOR(31 downto 0)  := (others => '0'); 
begin 

    process (a,b) 
    begin 
    result_ext <= std_logic_vector(signed('0' & a) + signed('0' & b)); 
    result  <= result_ext(result'left downto 0); 

    alu_out <= result; 
    end process; 
end Behavioral; 

與試驗檯：

-- TestBench Template 

    LIBRARY ieee; 
    USE ieee.std_logic_1164.ALL; 
    USE ieee.numeric_std.ALL; 

    ENTITY testbench IS 
    END testbench; 

    ARCHITECTURE behavior OF testbench IS   

    signal a : STD_LOGIC_VECTOR(31 downto 0); 
    signal b : STD_LOGIC_VECTOR(31 downto 0); 
    signal alu_out : STD_LOGIC_VECTOR(31 downto 0); 
    BEGIN 
    ADDER : entity work.adder port map(
     a => a, 
     b => b, 
     alu_out => alu_out 
    ); 



    -- Test Bench Statements 
    tb : PROCESS 
    BEGIN 

     a <= B"0000_0000_0000_0000_0000_0000_0111_1010"; 
     b <= B"0000_0000_0000_0000_0000_0000_0000_1011"; 

     wait for 100 ns; -- wait until global set/reset completes 

     report "alu_out = " & integer'image(to_integer(signed(alu_out))); 

     wait; -- will wait forever 
    END PROCESS tb; 
    -- End Test Bench 

    END; 

我得到報告輸出：

Finished circuit initialization process. 
at 100 ns: Note: alu_out = 0 (/testbench/). 

如果我不初始化結果信號我得到未定義。所以問題是我最終沒有得到 的結果。

我用的iSim和賽靈思。

另外，如果有人有一些很好的鏈接到VHDL的一些簡短而有效的材料，請隨時張貼它。

Answer 1

問題在於，如果您希望在進程的該循環中使用它們的立即值，則可以使用result和result_ext的信號。變量會立即更新，您可以在流程的當前週期中訪問它們的值。

嘗試了這一點，我認爲它解決您所遇到的問題：

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use ieee.std_logic_unsigned.all; 
use ieee.numeric_std.all; 

entity adder is 
    Port (a : in STD_LOGIC_VECTOR(31 downto 0); 
      b : in STD_LOGIC_VECTOR(31 downto 0); 
      alu_out : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0') 
      ); 
end adder; 

architecture Behavioral of adder is 


begin 

    process (a,b) 
    variable result_ext:STD_LOGIC_VECTOR(32 downto 0) := (others => '0'); 
    variable result:STD_LOGIC_VECTOR(31 downto 0); 
    begin 
    result_ext := std_logic_vector(signed('0' & a) + signed('0' & b)); 
    result  := result_ext(result'left downto 0); 

    alu_out <= result; 
    end process; 
end Behavioral; 

至於閱讀材料中，VHDL食譜是不壞：VHDL Cookbook

Answer 2

以彼得代碼：

• 更新輸入寬度的靈活性
• 只是numeric_std
• 保持進位

給出了這樣的：

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use ieee.numeric_std.all; 

entity adder is 
    generic (width : integer := 32) 
    Port (a  : in signed(width-1 downto 0); 
      b  : in signed(width-1 downto 0); 
      alu_out : out signed(width downto 0) := (others => '0'); 
      ); 
end adder; 

architecture synth of adder is 
begin 
    process (a,b) 
    begin 
    alu_out <= resize(a,alu_out'length) + b; 
    end process; 
end Behavioral;