VHDL：11總線之間的多路複用器8位寬輸出

Question

我收到了這個問題作爲一個面試前的問題「繪製一個圖表並寫滿足以下要求的模塊的VHDL代碼： a。完全同步 b。Muxes在每條總線8位寬的11條總線之間 c。有2個週期的延遲 d。針對最大時鐘頻率進行了優化。

我一直在嘗試自己做我自己讀舊筆記和作業，我在大學裏做過，但我不認爲我在這條正確的軌道上。我的代碼洙遠遠下面貼：

library IEEE; 
use IEEE.STD_LOGIC_1164.all; 

entity Mux is 
port(

A: in STD_LOGIC_vector(7 downto 0); 
    B: in STD_LOGIC_vector(7 downto 0); 
    C: in STD_LOGIC_vector(7 downto 0); 
    D: in STD_LOGIC_vector(7 downto 0); 
    E: in STD_LOGIC_vector(7 downto 0); 
    F: in STD_LOGIC_vector(7 downto 0); 
    G: in STD_LOGIC_vector(7 downto 0); 
    H: in STD_LOGIC_vector(7 downto 0); 
    I: in STD_LOGIC_vector(7 downto 0); 
    J: in STD_LOGIC_vector(7 downto 0); 
    K: in STD_LOGIC_vector(7 downto 0); 
S0: in std_LOGIC_vector(3 downto 0); 

Z: out STD_LOGIC_vector(7 downto 0) 
); 
end Mux; 
architecture func of Mux is 
begin 
process (A,B,C,D,E,F,G,H,I,J,K,S0) 
begin 

    if S0="0001" then 
     Z<= A; 
    elsif S0="0010" then 
     Z<= B; 
    elsif S0="0011" then 
     Z<= C; 
    elsif S0="0100" then 
     Z<= D; 
    elsif S0="0101" then 
     Z<= E; 
    elsif S0="0110" then 
     Z<= F; 
    elsif S0="0111" then 
     Z<= G; 
    elsif S0="1000" then 
     Z<= H; 
    elsif S0="1001" then 
     Z<= I; 
    elsif S0="1010" then 
     Z<= J; 
    elsif S0="1011" then 
     Z<= K; 
    else 
     Z<=A; 
    end if; 


end process; 
end func; 

，這是代碼我有我的第二個文件：

LIBRARY ieee; 
USE ieee.std_logic_1164.ALL; 
use IEEE.std_logic_arith.all; 
entity mux11test is 
end entity mux11test; 
architecture test of mux11test is 
    signal T_A: STD_LOGIC_vector(7 downto 0):="00000001"; 
    signal T_B: STD_LOGIC_vector(7 downto 0):="00000010"; 
    signal T_C: STD_LOGIC_vector(7 downto 0):="00000011"; 
    signal T_D: STD_LOGIC_vector(7 downto 0):="00000100"; 
    signal T_E: STD_LOGIC_vector(7 downto 0):="00000101"; 
    signal T_F: STD_LOGIC_vector(7 downto 0):="00000110"; 
    signal T_G: STD_LOGIC_vector(7 downto 0):="00000111"; 
    signal T_H: STD_LOGIC_vector(7 downto 0):="00001000"; 
    signal T_I: STD_LOGIC_vector(7 downto 0):="00001001"; 
    signal T_J: STD_LOGIC_vector(7 downto 0):="00001010"; 
    signal T_K: STD_LOGIC_vector(7 downto 0):="00001011"; 

    signal T_S: STD_LOGIC_vector(3 downto 0); 
signal T_Z: STD_LOGIC_vector(7 downto 0); 

component mux11 IS 
port(

A: in STD_LOGIC_vector(7 downto 0); 
    B: in STD_LOGIC_vector(7 downto 0); 
    C: in STD_LOGIC_vector(7 downto 0); 
    D: in STD_LOGIC_vector(7 downto 0); 
    E: in STD_LOGIC_vector(7 downto 0); 
    F: in STD_LOGIC_vector(7 downto 0); 
    G: in STD_LOGIC_vector(7 downto 0); 
    H: in STD_LOGIC_vector(7 downto 0); 
    I: in STD_LOGIC_vector(7 downto 0); 
    J: in STD_LOGIC_vector(7 downto 0); 
    K: in STD_LOGIC_vector(7 downto 0); 
S0: in std_LOGIC_vector(3 downto 0); 

Z: out STD_LOGIC_vector(7 downto 0) 
); 
END COMPONENT ; 
signal clk : std_LOGIC; 
constant clk_period: time:=100ns; 
begin 

umux: Mux11 port map(T_A,T_B,T_C,T_D,T_E,T_F,T_G,T_H,T_I,T_J,T_K,T_S,T_Z); 
clk_process:process 
begin 
clk<='0'; 
wait for clk_period/2; 
clk <='1'; 
wait for clk_period/2; 
end process; 
PROCESS 
begin 
if T_S="0001" then 
    T_Z <= T_A ; 
elsif T_S="0010" then 
T_Z <= T_B ; wait for 100 ns; 
elsif T_S="0011" then 
T_Z <= T_C ; wait for 100 ns; 
elsif T_S="0100" then 
T_Z <= T_D ; wait for 100 ns; 
elsif T_S="0101" then 
T_Z <=T_E ; wait for 100 ns; 
elsif T_S="0110" then 
T_Z <= T_F ; wait for 100 ns; 
    elsif T_S="0111" then 
T_Z <= T_G ; wait for 100 ns; 
    elsif T_S="1000" then 
T_Z <= T_H ; wait for 100 ns; 
elsif T_S="1001" then 
T_Z <= T_I ; wait for 100 ns; 
elsif T_S="1010" then 
T_Z <= T_J ; wait for 100 ns; 
elsif T_S="1011" then 
T_Z <= T_K ; wait for 100 ns; 


wait; 

end if; 
end PROCESS; 

end architecture test; 

是否有任何人誰可以告訴我，如果即時通訊在正確的道路上，如果這是完全同步的，我將如何開始執行或確定2個週期的延遲？

Answer 1

我試着寫一個明確的答案來幫助你。

首先你需要一個時鐘在你的設計中，我們稱之爲clk。

entity Mux is 
port(

    clk: in std_logic; 
    A: in STD_LOGIC_vector(7 downto 0); 
    B: in STD_LOGIC_vector(7 downto 0); 
    C: in STD_LOGIC_vector(7 downto 0); 
    D: in STD_LOGIC_vector(7 downto 0); 
    E: in STD_LOGIC_vector(7 downto 0); 
    F: in STD_LOGIC_vector(7 downto 0); 
    G: in STD_LOGIC_vector(7 downto 0); 
    H: in STD_LOGIC_vector(7 downto 0); 
    I: in STD_LOGIC_vector(7 downto 0); 
    J: in STD_LOGIC_vector(7 downto 0); 
    K: in STD_LOGIC_vector(7 downto 0); 
    S0: in std_LOGIC_vector(3 downto 0); 

    Z: out STD_LOGIC_vector(7 downto 0)); 

end Mux; 

當你使用同步過程的想法是總是更新你的時鐘邊緣的值。我們說上升的優勢。因此您的流程必須只對您的輸入clk敏感。

P : PROCESS (clk) 
BEGIN 
    IF (rising_edge(clk)) THEN 
    ... 
    END IF; 
END PROCESS; 

關於你的多路複用器，你的想法很好。但我會建議使用CASE聲明，因爲它比IFELSIF更容易閱讀。

CASE S0 IS 
    WHEN "0001" => Z <= A; 
    WHEN "0010" => Z <= B; 
    ... 
    WHEN "1011" => Z <= K; 
END CASE; 

編輯：因爲我忘了談論2個週期的延遲我會說兩個字。你需要兩個中間信號（即Z_i和Z_ii）。 Z_ii在一個時鐘週期後需要Z_i，Z在一個時鐘週期後需要Z_ii。

Z_ii <= Z_i; 
Z <= Z_ii; 

當然你需要在你的過程中驅動Z_i（而不是Z）。