如何使vivado上的led低電平有效

這個程序代表一個有限狀態機，帶有一個7段LED，它的計數爲5.我需要讓它處於低電平而不是高電平，但我只是不確定如何做到這一點。我也有測試臺。我知道最好總是使用時鐘語句，但我可以稍後處理。如何使vivado上的led低電平有效

`timescale 1ns/1ps 

//inputs, outputs 

module Counter(
    input u, 
    input clrn, 
    input clk, 
    output reg a, 
    output reg b, 
    output reg c, 
    output reg d, 
    output reg e, 
    output reg f, 
    output reg g); 

    reg [2:0] ns; //next state 
    reg [2:0] q; //present state 
//declaration of the states  
    parameter [2:0] S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100, S5 = 3'b101; 

    always @ (posedge clk or negedge clrn) 
    begin 
    if(~clrn) //if reset present state q goes to 0 
     q = S0; 
    else 
    begin 
     case(q) //tests present state 
      S0: 
      if (u==1) begin 
       ns = S1; 
       a = 1'b0; 
       b = 1'b1; 
       c = 1'b1; 
       d = 1'b0; 
       e = 1'b0; 
       f = 1'b0; 
       g = 1'b0; 
      end 
      else begin 
       ns = S5; 
       a = 1'b1; 
       b = 1'b0; 
       c = 1'b1; 
       d = 1'b1; 
       e = 1'b0; 
       f = 1'b1; 
       g = 1'b1; 
      end 

      S1: 
      if (u==1) begin 
       ns = S2; 
       a = 1'b1; 
       b = 1'b1; 
       c = 1'b0; 
       d = 1'b1; 
       e = 1'b1; 
       f = 1'b0; 
       g = 1'b1; 
      end 
      else begin 
       ns = S0; 
       a = 1'b1; 
       b = 1'b1; 
       c = 1'b1; 
       d = 1'b1; 
       e = 1'b1; 
       f = 1'b1; 
       g = 1'b0; 
      end 

      S2: 
      if (u==1) begin 
       ns = S3; 
       a = 1'b1; 
       b = 1'b1; 
       c = 1'b1; 
       d = 1'b1; 
       e = 1'b0; 
       f = 1'b0; 
       g = 1'b1; 
      end 
      else begin 
       ns = S1; 
       a = 1'b0; 
       b = 1'b1; 
       c = 1'b1; 
       d = 1'b0; 
       e = 1'b0; 
       f = 1'b0; 
       g = 1'b0; 
      end    

      S3: 
      if (u==1) begin 
       ns = S4; 
       a = 1'b0; 
       b = 1'b1; 
       c = 1'b1; 
       d = 1'b0; 
       e = 1'b0; 
       f = 1'b1; 
       g = 1'b1; 
      end 
      else begin 
       ns = S2; 
       a = 1'b1; 
       b = 1'b0; 
       c = 1'b1; 
       d = 1'b1; 
       e = 1'b0; 
       f = 1'b1; 
       g = 1'b1; 
      end 

      S4: 
      if (u==1) begin 
       ns = S5; 
       a = 1'b1; 
       b = 1'b0; 
       c = 1'b1; 
       d = 1'b1; 
       e = 1'b0; 
       f = 1'b1; 
       g = 1'b1; 
      end 
      else begin 
       ns = S3; 
       a = 1'b1; 
       b = 1'b1; 
       c = 1'b1; 
       d = 1'b1; 
       e = 1'b0; 
       f = 1'b0; 
       g = 1'b1; 
      end 

      S5: 
      if (u==1) begin 
       ns = S0; 
       a = 1'b1; 
       b = 1'b1; 
       c = 1'b1; 
       d = 1'b1; 
       e = 1'b1; 
       f = 1'b1; 
       g = 1'b0; 
      end 
      else begin 
       ns = S4; 
       a = 1'b0; 
       b = 1'b1; 
       c = 1'b1; 
       d = 1'b0; 
       e = 1'b0; 
       f = 1'b1; 
       g = 1'b1; 
      end 

     endcase 

     q = ns; 

    end 

    end 

endmodule

TESTBENCH：

`timescale 1ns/1ps 

module testbench; 

reg U, CLK, CLRN; 
wire A, B, C, D, E, F, G; 

Counter inst(

.clk (CLK), 
.u (U), 
.clrn (CLRN), 
.a (A), 
.b (B), 
.c (C), 
.d (D), 
.e (E), 
.f (F), 
.g (G)); 

initial 

begin //CLRN starts low, CLK starts high, U starts high 

CLRN = 1'b0; 

CLK = 1'b1; 

U = 1'b1; 

//CLK will change every ns 

#1 CLRN = 1'b1; 
CLK = 1'b0; 

#1 CLK = 1'b1; 

#1 CLK = 1'b0; 

#1 CLK = 1'b1; 

#1 CLK = 1'b0; 

#1 CLK = 1'b1; 

#1 CLK = 1'b0; 

#1 CLK = 1'b1; 

#1 CLK = 1'b0; 

#1 CLK = 1'b1; 

#1 CLK = 1'b0; 

#1 CLK = 1'b1; 

#1 CLK = 1'b0; 

#1 CLK = 1'b1; 

#1 CLK = 1'b0; 

#1 CLK = 1'b1; 

#1 CLK = 1'b0; //On the ns 17 u will change to low 
U = 1'b0; 

#1 CLK = 1'b1; 

#1 CLK = 1'b0; 

#1 CLK = 1'b1; 

#1 CLK = 1'b0; 

#1 CLK = 1'b1; 

#1 CLK = 1'b0; 

#1 CLK = 1'b1; 

#1 CLK = 1'b0; 

#1 CLK = 1'b1; 

#1 CLK = 1'b0; 

#1 CLK = 1'b1; 

#1 CLK = 1'b0; 

#1 CLK = 1'b1; 

#1 CLK = 1'b0; 

#1 CLK = 1'b1; 

#1 CLK = 1'b0; 

#1 CLK = 1'b1; 

#1 CLK = 1'b0; 

#1 CLK = 1'b1; 

#1 CLK = 1'b0; 

#1 CLK = 1'b1; 

#1 CLK = 1'b0; 

#1 CLK = 1'b1; 

end 

endmodule

非常感謝您！

來源

2017-03-16 Adam

最快的方法是簡單地更改每個狀態的直通分配。

在第一種情況下，你有這個

  a = 1'b0; 
      b = 1'b1; 
      c = 1'b1; 
      d = 1'b0; 
      e = 1'b0; 
      f = 1'b0; 
      g = 1'b0;

更改它這一點，你將扭轉輸出的極性。

  a = 1'b1; // old setting 1'b0; 
      b = 1'b0; // old setting 1'b1; 
      c = 1'b0; // old setting 1'b1; 
      d = 1'b1; // old setting 1'b0; 
      e = 1'b1; // old setting 1'b0; 
      f = 1'b1; // old setting 1'b0; 
      g = 1'b1; // old setting 1'b0;

或者，可以使新的寄存器

reg a_n, b_n, c_n, d_n, e_n, f_n, g_n;

然後再通過所有的寄存器分配和改變他們對這些新註冊的名字

a_n = 1'b0; 
b_n = 1'b1; 
c_n = 1'b1; 
d_n = 1'b0; 
e_n = 1'b0; 
f_n = 1'b0; 
g_n = 1'b0;

然後作出一個新的總區塊

// Invert the register outputs 
always @ (a_n or b_n or c_n or d_n or e_n or f_n or g_n) 
begin 
    a <= ~a_n; 
    b <= ~b_n; 
    c <= ~c_n; 
    d <= ~d_n; 
    e <= ~e_n; 
    f <= ~f_n; 
    g <= ~g_n; 
end

來源

2017-03-16 05:21:09

如何使vivado上的led低電平有效

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